105 lines
3.3 KiB
Rust
105 lines
3.3 KiB
Rust
use crate::hal;
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use hal::rcc::{rec, CoreClocks, ResetEnable};
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pub enum Channel {
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One,
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Two,
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}
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pub struct HighResTimerE {
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master: hal::stm32::HRTIM_MASTER,
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timer: hal::stm32::HRTIM_TIME,
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common: hal::stm32::HRTIM_COMMON,
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clocks: CoreClocks,
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}
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impl HighResTimerE {
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pub fn new(
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timer_regs: hal::stm32::HRTIM_TIME,
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master_regs: hal::stm32::HRTIM_MASTER,
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common_regs: hal::stm32::HRTIM_COMMON,
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clocks: CoreClocks,
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prec: rec::Hrtim,
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) -> Self {
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prec.reset().enable();
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Self {
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master: master_regs,
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timer: timer_regs,
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common: common_regs,
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clocks,
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}
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}
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pub fn configure_single_shot(
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&mut self,
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channel: Channel,
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set_duration: f32,
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set_offset: f32,
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) {
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// Disable the timer before configuration.
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self.master.mcr.modify(|_, w| w.tecen().clear_bit());
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// Configure the desired timer for single shot mode with set and reset of the specified
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// channel at the desired durations. The HRTIM is on APB2 (D2 domain), and the kernel clock
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// is the APB bus clock.
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let minimum_duration = set_duration + set_offset;
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let source_frequency: u32 = self.clocks.timy_ker_ck().0;
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let source_cycles = (minimum_duration * source_frequency as f32) as u32 + 1;
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// Determine the clock divider, which may be 1, 2, or 4. We will choose a clock divider that
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// allows us the highest resolution per tick, so lower dividers are favored.
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let divider: u8 = if source_cycles < 0xFFDF {
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1
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} else if (source_cycles / 2) < 0xFFDF {
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2
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} else if (source_cycles / 4) < 0xFFDF {
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4
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} else {
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panic!("Unattainable timing parameters!");
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};
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// The period register must be greater than or equal to 3 cycles.
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let period = (source_cycles / divider as u32) as u16;
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assert!(period > 2);
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// We now have the prescaler and the period registers. Configure the timer.
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self.timer
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.timecr
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.modify(|_, w| unsafe { w.ck_pscx().bits(divider + 4) });
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self.timer.perer.write(|w| unsafe { w.perx().bits(period) });
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// Configure the comparator 1 level.
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let offset = (set_offset * source_frequency as f32) as u16;
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self.timer
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.cmp1er
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.write(|w| unsafe { w.cmp1x().bits(offset) });
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// Configure the set/reset signals.
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// Set on compare with CMP1, reset upon reaching PER
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match channel {
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Channel::One => {
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self.timer.sete1r.write(|w| w.cmp1().set_bit());
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self.timer.rste1r.write(|w| w.per().set_bit());
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self.common.oenr.write(|w| w.te1oen().set_bit());
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}
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Channel::Two => {
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self.timer.sete2r.write(|w| w.cmp1().set_bit());
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self.timer.rste2r.write(|w| w.per().set_bit());
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self.common.oenr.write(|w| w.te2oen().set_bit());
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}
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}
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// Enable the timer now that it is configured.
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self.master.mcr.modify(|_, w| w.tecen().set_bit());
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}
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pub fn trigger(&mut self) {
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// Generate a reset event to force the timer to start counting.
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self.common.cr2.write(|w| w.terst().set_bit());
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}
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}
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