1044 lines
35 KiB
Rust
1044 lines
35 KiB
Rust
///! Stabilizer hardware configuration
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///!
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///! This file contains all of the hardware-specific configuration of Stabilizer.
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use core::sync::atomic::{self, AtomicBool, Ordering};
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use core::{ptr, slice};
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use stm32h7xx_hal::{
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self as hal,
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ethernet::{self, PHY},
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prelude::*,
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};
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use smoltcp_nal::smoltcp;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use super::{
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adc, afe, cycle_counter::CycleCounter, dac, design_parameters, eeprom,
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input_stamper::InputStamper, pounder, pounder::dds_output::DdsOutput,
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system_timer, timers, DigitalInput0, DigitalInput1, EthernetPhy,
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NetworkStack, AFE0, AFE1,
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};
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const NUM_TCP_SOCKETS: usize = 4;
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const NUM_UDP_SOCKETS: usize = 1;
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const NUM_SOCKETS: usize = NUM_UDP_SOCKETS + NUM_TCP_SOCKETS;
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pub struct NetStorage {
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pub ip_addrs: [smoltcp::wire::IpCidr; 1],
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// Note: There is an additional socket set item required for the DHCP socket.
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pub sockets:
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[Option<smoltcp::socket::SocketSetItem<'static>>; NUM_SOCKETS + 1],
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pub tcp_socket_storage: [TcpSocketStorage; NUM_TCP_SOCKETS],
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pub udp_socket_storage: [UdpSocketStorage; NUM_UDP_SOCKETS],
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pub neighbor_cache:
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[Option<(smoltcp::wire::IpAddress, smoltcp::iface::Neighbor)>; 8],
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pub routes_cache:
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[Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 8],
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}
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pub struct UdpSocketStorage {
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rx_storage: [u8; 1024],
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tx_storage: [u8; 2048],
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tx_metadata:
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[smoltcp::storage::PacketMetadata<smoltcp::wire::IpEndpoint>; 10],
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rx_metadata:
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[smoltcp::storage::PacketMetadata<smoltcp::wire::IpEndpoint>; 10],
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}
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impl UdpSocketStorage {
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const fn new() -> Self {
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Self {
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rx_storage: [0; 1024],
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tx_storage: [0; 2048],
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tx_metadata: [smoltcp::storage::PacketMetadata::<
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smoltcp::wire::IpEndpoint,
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>::EMPTY; 10],
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rx_metadata: [smoltcp::storage::PacketMetadata::<
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smoltcp::wire::IpEndpoint,
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>::EMPTY; 10],
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}
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}
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}
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#[derive(Copy, Clone)]
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pub struct TcpSocketStorage {
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rx_storage: [u8; 1024],
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tx_storage: [u8; 1024],
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}
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impl TcpSocketStorage {
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const fn new() -> Self {
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Self {
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rx_storage: [0; 1024],
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tx_storage: [0; 1024],
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}
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}
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}
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impl Default for NetStorage {
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fn default() -> Self {
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NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [smoltcp::wire::IpCidr::Ipv6(
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smoltcp::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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routes_cache: [None; 8],
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sockets: [None, None, None, None, None, None],
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tcp_socket_storage: [TcpSocketStorage::new(); NUM_TCP_SOCKETS],
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udp_socket_storage: [UdpSocketStorage::new(); NUM_UDP_SOCKETS],
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}
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}
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}
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/// The available networking devices on Stabilizer.
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pub struct NetworkDevices {
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pub stack: NetworkStack,
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pub phy: EthernetPhy,
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pub mac_address: smoltcp::wire::EthernetAddress,
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}
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/// The available hardware interfaces on Stabilizer.
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pub struct StabilizerDevices {
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pub afes: (AFE0, AFE1),
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pub adcs: (adc::Adc0Input, adc::Adc1Input),
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pub dacs: (dac::Dac0Output, dac::Dac1Output),
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pub timestamper: InputStamper,
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pub adc_dac_timer: timers::SamplingTimer,
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pub timestamp_timer: timers::TimestampTimer,
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pub net: NetworkDevices,
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pub cycle_counter: CycleCounter,
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pub digital_inputs: (DigitalInput0, DigitalInput1),
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}
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/// The available Pounder-specific hardware interfaces.
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pub struct PounderDevices {
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pub pounder: pounder::PounderDevices,
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pub dds_output: DdsOutput,
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#[cfg(feature = "pounder_v1_1")]
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pub timestamper: pounder::timestamp::Timestamper,
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}
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#[link_section = ".sram3.eth"]
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/// Static storage for the ethernet DMA descriptor ring.
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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/// Setup ITCM and load its code from flash.
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///
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/// For portability and maintainability this is implemented in Rust.
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/// Since this is implemented in Rust the compiler may assume that bss and data are set
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/// up already. There is no easy way to ensure this implementation will never need bss
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/// or data. Hence we can't safely run this as the cortex-m-rt `pre_init` hook before
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/// bss/data is setup.
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///
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/// Calling (through IRQ or directly) any code in ITCM before having called
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/// this method is undefined.
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fn load_itcm() {
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extern "C" {
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static mut __sitcm: u32;
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static mut __eitcm: u32;
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static mut __siitcm: u32;
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}
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// NOTE(unsafe): Assuming the address symbols from the linker as well as
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// the source instruction data are all valid, this is safe as it only
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// copies linker-prepared data to where the code expects it to be.
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// Calling it multiple times is safe as well.
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unsafe {
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// ITCM is enabled on reset on our CPU but might not be on others.
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// Keep for completeness.
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const ITCMCR: *mut u32 = 0xE000_EF90usize as _;
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ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1);
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// Ensure ITCM is enabled before loading.
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atomic::fence(Ordering::SeqCst);
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let len =
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(&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize;
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let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len);
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let src = slice::from_raw_parts(&__siitcm as *const _, len);
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// Load code into ITCM.
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dst.copy_from_slice(src);
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}
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// Ensure ITCM is loaded before potentially executing any instructions from it.
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atomic::fence(Ordering::SeqCst);
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cortex_m::asm::dsb();
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cortex_m::asm::isb();
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}
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/// Configure the stabilizer hardware for operation.
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///
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/// # Note
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/// Refer to [design_parameters::TIMER_FREQUENCY] to determine the frequency of the sampling timer.
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///
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/// # Args
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/// * `core` - The RTIC core for configuring the cortex-M core of the device.
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/// * `device` - The microcontroller peripherals to be configured.
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/// * `batch_size` - The size of each ADC/DAC batch.
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/// * `sample_ticks` - The number of timer ticks between each sample.
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///
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/// # Returns
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/// (stabilizer, pounder) where `stabilizer` is a `StabilizerDevices` structure containing all
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/// stabilizer hardware interfaces in a disabled state. `pounder` is an `Option` containing
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/// `Some(devices)` if pounder is detected, where `devices` is a `PounderDevices` structure
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/// containing all of the pounder hardware interfaces in a disabled state.
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pub fn setup(
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mut core: rtic::Peripherals,
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device: stm32h7xx_hal::stm32::Peripherals,
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batch_size: usize,
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sample_ticks: u32,
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) -> (StabilizerDevices, Option<PounderDevices>) {
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let pwr = device.PWR.constrain();
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let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
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device.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Clear reset flags.
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device.RCC.rsr.write(|w| w.rmvf().set_bit());
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// Select the PLLs for SPI.
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device
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.RCC
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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device.RCC.d1ccipr.modify(|_, w| w.qspisel().rcc_hclk3());
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let rcc = device.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &device.SYSCFG);
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// Set up RTT logging
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{
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// Enable debug during WFE/WFI-induced sleep
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device.DBGMCU.cr.modify(|_, w| w.dbgsleep_d1().set_bit());
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// Set up RTT channel to use for `rprintln!()` as "best effort".
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// This removes a critical section around the logging and thus allows
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// high-prio tasks to always interrupt at low latency.
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// It comes at a cost:
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// If a high-priority tasks preempts while we are logging something,
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// and if we then also want to log from within that high-preiority task,
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// the high-prio log message will be lost.
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let channels = rtt_target::rtt_init_default!();
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// Note(unsafe): The closure we pass does not establish a critical section
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// as demanded but it does ensure synchronization and implements a lock.
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unsafe {
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rtt_target::set_print_channel_cs(
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channels.up.0,
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&((|arg, f| {
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static LOCKED: AtomicBool = AtomicBool::new(false);
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if LOCKED.compare_exchange_weak(
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false,
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true,
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Ordering::Acquire,
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Ordering::Relaxed,
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) == Ok(false)
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{
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f(arg);
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LOCKED.store(false, Ordering::Release);
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}
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}) as rtt_target::CriticalSectionFunc),
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);
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}
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static LOGGER: rtt_logger::RTTLogger =
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rtt_logger::RTTLogger::new(log::LevelFilter::Info);
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log::set_logger(&LOGGER)
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.map(|()| log::set_max_level(log::LevelFilter::Trace))
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.unwrap();
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log::info!("Starting");
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}
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// Before being able to call any code in ITCM, load that code from flash.
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load_itcm();
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// Set up the system timer for RTIC scheduling.
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{
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let tim15 =
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device
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.TIM15
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.timer(10.khz(), ccdr.peripheral.TIM15, &ccdr.clocks);
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system_timer::SystemTimer::initialize(tim15);
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}
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let mut delay = asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz(
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ccdr.clocks.c_ck().0,
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));
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let gpioa = device.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = device.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = device.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = device.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = device.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = device.GPIOF.split(ccdr.peripheral.GPIOF);
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let mut gpiog = device.GPIOG.split(ccdr.peripheral.GPIOG);
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let dma_streams =
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hal::dma::dma::StreamsTuple::new(device.DMA1, ccdr.peripheral.DMA1);
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// Configure timer 2 to trigger conversions for the ADC
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let mut sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer2 =
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device
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.TIM2
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.timer(1.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer2.pause();
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timer2.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut sampling_timer = timers::SamplingTimer::new(timer2);
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sampling_timer.set_period_ticks(sample_ticks - 1);
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// The sampling timer is used as the master timer for the shadow-sampling timer. Thus,
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// it generates a trigger whenever it is enabled.
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sampling_timer
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};
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let mut shadow_sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer3 =
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device
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.TIM3
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.timer(1.khz(), ccdr.peripheral.TIM3, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer3.pause();
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timer3.reset_counter();
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timer3.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut shadow_sampling_timer =
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timers::ShadowSamplingTimer::new(timer3);
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shadow_sampling_timer.set_period_ticks(sample_ticks as u16 - 1);
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// The shadow sampling timer is a slave-mode timer to the sampling timer. It should
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// always be in-sync - thus, we configure it to operate in slave mode using "Trigger
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// mode".
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// For TIM3, TIM2 can be made the internal trigger connection using ITR1. Thus, the
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// SamplingTimer start now gates the start of the ShadowSamplingTimer.
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shadow_sampling_timer.set_slave_mode(
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timers::TriggerSource::Trigger1,
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timers::SlaveMode::Trigger,
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);
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shadow_sampling_timer
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};
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let sampling_timer_channels = sampling_timer.channels();
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let shadow_sampling_timer_channels = shadow_sampling_timer.channels();
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let mut timestamp_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer5 =
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device
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.TIM5
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.timer(1.khz(), ccdr.peripheral.TIM5, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer5.pause();
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timer5.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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// The timestamp timer runs at the counter cycle period as the sampling timers.
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// To accomodate this, we manually set the prescaler identical to the sample
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// timer, but use maximum overflow period.
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let mut timer = timers::TimestampTimer::new(timer5);
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// TODO: Check hardware synchronization of timestamping and the sampling timers
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// for phase shift determinism.
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timer.set_period_ticks(u32::MAX);
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timer
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};
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let timestamp_timer_channels = timestamp_timer.channels();
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// Configure the SPI interfaces to the ADCs and DACs.
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let adcs = {
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let adc0 = {
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let spi_miso = gpiob
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.pb14
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiob
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.pb10
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_nss = gpiob
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.pb9
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.into_alternate_af5()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.hardware_cs(hal::spi::HardwareCS {
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mode: hal::spi::HardwareCSMode::WordTransaction,
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assertion_delay: design_parameters::ADC_SETUP_TIME,
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polarity: hal::spi::Polarity::IdleHigh,
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})
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.communication_mode(hal::spi::CommunicationMode::Receiver);
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let spi: hal::spi::Spi<_, _, u16> = device.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi, spi_nss),
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config,
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design_parameters::ADC_DAC_SCK_MAX,
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ccdr.peripheral.SPI2,
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&ccdr.clocks,
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);
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adc::Adc0Input::new(
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spi,
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dma_streams.0,
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dma_streams.1,
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dma_streams.2,
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sampling_timer_channels.ch1,
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shadow_sampling_timer_channels.ch1,
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batch_size,
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)
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};
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let adc1 = {
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let spi_miso = gpiob
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.pb4
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioc
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.pc10
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let spi_nss = gpioa
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.pa15
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.into_alternate_af6()
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.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.hardware_cs(hal::spi::HardwareCS {
|
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mode: hal::spi::HardwareCSMode::WordTransaction,
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assertion_delay: design_parameters::ADC_SETUP_TIME,
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polarity: hal::spi::Polarity::IdleHigh,
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})
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.communication_mode(hal::spi::CommunicationMode::Receiver);
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let spi: hal::spi::Spi<_, _, u16> = device.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi, spi_nss),
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config,
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design_parameters::ADC_DAC_SCK_MAX,
|
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ccdr.peripheral.SPI3,
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&ccdr.clocks,
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);
|
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|
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adc::Adc1Input::new(
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spi,
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dma_streams.3,
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dma_streams.4,
|
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dma_streams.5,
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sampling_timer_channels.ch2,
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shadow_sampling_timer_channels.ch2,
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batch_size,
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)
|
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};
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(adc0, adc1)
|
|
};
|
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|
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let dacs = {
|
|
let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap();
|
|
let _dac0_ldac_n =
|
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gpioe.pe11.into_push_pull_output().set_low().unwrap();
|
|
let _dac1_ldac_n =
|
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gpioe.pe15.into_push_pull_output().set_low().unwrap();
|
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|
|
let dac0_spi = {
|
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let spi_miso = gpioe
|
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.pe5
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpioe
|
|
.pe2
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_nss = gpioe
|
|
.pe4
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
})
|
|
.hardware_cs(hal::spi::HardwareCS {
|
|
mode: hal::spi::HardwareCSMode::WordTransaction,
|
|
assertion_delay: 0.0,
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
})
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
.swap_mosi_miso();
|
|
|
|
device.SPI4.spi(
|
|
(spi_sck, spi_miso, hal::spi::NoMosi, spi_nss),
|
|
config,
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
ccdr.peripheral.SPI4,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let dac1_spi = {
|
|
let spi_miso = gpiof
|
|
.pf8
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpiof
|
|
.pf7
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_nss = gpiof
|
|
.pf6
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
})
|
|
.hardware_cs(hal::spi::HardwareCS {
|
|
mode: hal::spi::HardwareCSMode::WordTransaction,
|
|
assertion_delay: 0.0,
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
})
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
.swap_mosi_miso();
|
|
|
|
device.SPI5.spi(
|
|
(spi_sck, spi_miso, hal::spi::NoMosi, spi_nss),
|
|
config,
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
ccdr.peripheral.SPI5,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let dac0 = dac::Dac0Output::new(
|
|
dac0_spi,
|
|
dma_streams.6,
|
|
sampling_timer_channels.ch3,
|
|
batch_size,
|
|
);
|
|
let dac1 = dac::Dac1Output::new(
|
|
dac1_spi,
|
|
dma_streams.7,
|
|
sampling_timer_channels.ch4,
|
|
batch_size,
|
|
);
|
|
(dac0, dac1)
|
|
};
|
|
|
|
let afes = {
|
|
let afe0 = {
|
|
let a0_pin = gpiof.pf2.into_push_pull_output();
|
|
let a1_pin = gpiof.pf5.into_push_pull_output();
|
|
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
|
|
};
|
|
|
|
let afe1 = {
|
|
let a0_pin = gpiod.pd14.into_push_pull_output();
|
|
let a1_pin = gpiod.pd15.into_push_pull_output();
|
|
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
|
|
};
|
|
|
|
(afe0, afe1)
|
|
};
|
|
|
|
let input_stamper = {
|
|
let trigger = gpioa.pa3.into_alternate_af2();
|
|
InputStamper::new(trigger, timestamp_timer_channels.ch4)
|
|
};
|
|
|
|
let digital_inputs = {
|
|
let di0 = gpiog.pg9.into_floating_input();
|
|
let di1 = gpioc.pc15.into_floating_input();
|
|
(di0, di1)
|
|
};
|
|
|
|
let mut eeprom_i2c = {
|
|
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
|
|
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
|
|
device.I2C2.i2c(
|
|
(scl, sda),
|
|
100.khz(),
|
|
ccdr.peripheral.I2C2,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Configure ethernet pins.
|
|
{
|
|
// Reset the PHY before configuring pins.
|
|
let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
|
|
eth_phy_nrst.set_low().unwrap();
|
|
delay.delay_us(200u8);
|
|
eth_phy_nrst.set_high().unwrap();
|
|
let _rmii_ref_clk = gpioa
|
|
.pa1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdio = gpioa
|
|
.pa2
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_mdc = gpioc
|
|
.pc1
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_crs_dv = gpioa
|
|
.pa7
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd0 = gpioc
|
|
.pc4
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_rxd1 = gpioc
|
|
.pc5
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_tx_en = gpiob
|
|
.pb11
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd0 = gpiob
|
|
.pb12
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let _rmii_txd1 = gpiog
|
|
.pg14
|
|
.into_alternate_af11()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
}
|
|
|
|
let mac_addr = smoltcp::wire::EthernetAddress(eeprom::read_eui48(
|
|
&mut eeprom_i2c,
|
|
&mut delay,
|
|
));
|
|
log::info!("EUI48: {}", mac_addr);
|
|
|
|
let network_devices = {
|
|
// Configure the ethernet controller
|
|
let (eth_dma, eth_mac) = unsafe {
|
|
ethernet::new_unchecked(
|
|
device.ETHERNET_MAC,
|
|
device.ETHERNET_MTL,
|
|
device.ETHERNET_DMA,
|
|
&mut DES_RING,
|
|
mac_addr,
|
|
ccdr.peripheral.ETH1MAC,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
// Reset and initialize the ethernet phy.
|
|
let mut lan8742a =
|
|
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
|
|
lan8742a.phy_reset();
|
|
lan8742a.phy_init();
|
|
|
|
unsafe { ethernet::enable_interrupt() };
|
|
|
|
// Note(unwrap): The hardware configuration function is only allowed to be called once.
|
|
// Unwrapping is intended to panic if called again to prevent re-use of global memory.
|
|
let store =
|
|
cortex_m::singleton!(: NetStorage = NetStorage::default()).unwrap();
|
|
|
|
store.ip_addrs[0] = smoltcp::wire::IpCidr::new(
|
|
smoltcp::wire::IpAddress::Ipv4(
|
|
smoltcp::wire::Ipv4Address::UNSPECIFIED,
|
|
),
|
|
0,
|
|
);
|
|
|
|
let mut routes =
|
|
smoltcp::iface::Routes::new(&mut store.routes_cache[..]);
|
|
routes
|
|
.add_default_ipv4_route(smoltcp::wire::Ipv4Address::UNSPECIFIED)
|
|
.unwrap();
|
|
|
|
let neighbor_cache =
|
|
smoltcp::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
|
|
|
|
let interface = smoltcp::iface::InterfaceBuilder::new(eth_dma)
|
|
.ethernet_addr(mac_addr)
|
|
.neighbor_cache(neighbor_cache)
|
|
.ip_addrs(&mut store.ip_addrs[..])
|
|
.routes(routes)
|
|
.finalize();
|
|
|
|
let sockets = {
|
|
let mut sockets =
|
|
smoltcp::socket::SocketSet::new(&mut store.sockets[..]);
|
|
|
|
for storage in store.tcp_socket_storage[..].iter_mut() {
|
|
let tcp_socket = {
|
|
let rx_buffer = smoltcp::socket::TcpSocketBuffer::new(
|
|
&mut storage.rx_storage[..],
|
|
);
|
|
let tx_buffer = smoltcp::socket::TcpSocketBuffer::new(
|
|
&mut storage.tx_storage[..],
|
|
);
|
|
|
|
smoltcp::socket::TcpSocket::new(rx_buffer, tx_buffer)
|
|
};
|
|
sockets.add(tcp_socket);
|
|
}
|
|
|
|
for storage in store.udp_socket_storage[..].iter_mut() {
|
|
let udp_socket = {
|
|
let rx_buffer = smoltcp::socket::UdpSocketBuffer::new(
|
|
&mut storage.rx_metadata[..],
|
|
&mut storage.rx_storage[..],
|
|
);
|
|
let tx_buffer = smoltcp::socket::UdpSocketBuffer::new(
|
|
&mut storage.tx_metadata[..],
|
|
&mut storage.tx_storage[..],
|
|
);
|
|
|
|
smoltcp::socket::UdpSocket::new(rx_buffer, tx_buffer)
|
|
};
|
|
sockets.add(udp_socket);
|
|
}
|
|
|
|
sockets.add(smoltcp::socket::Dhcpv4Socket::new());
|
|
|
|
sockets
|
|
};
|
|
|
|
let random_seed = {
|
|
let mut rng =
|
|
device.RNG.constrain(ccdr.peripheral.RNG, &ccdr.clocks);
|
|
let mut data = [0u8; 4];
|
|
rng.fill(&mut data).unwrap();
|
|
data
|
|
};
|
|
|
|
let mut stack = smoltcp_nal::NetworkStack::new(interface, sockets);
|
|
|
|
stack.seed_random_port(&random_seed);
|
|
|
|
NetworkDevices {
|
|
stack,
|
|
phy: lan8742a,
|
|
mac_address: mac_addr,
|
|
}
|
|
};
|
|
|
|
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
|
|
let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
|
|
let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
|
|
let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
|
|
|
|
fp_led_0.set_low().unwrap();
|
|
fp_led_1.set_low().unwrap();
|
|
fp_led_2.set_low().unwrap();
|
|
fp_led_3.set_low().unwrap();
|
|
|
|
// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
|
|
let pounder_pgood = gpiob.pb13.into_pull_down_input();
|
|
delay.delay_ms(2u8);
|
|
let pounder = if pounder_pgood.is_high().unwrap() {
|
|
log::info!("Found Pounder");
|
|
|
|
let io_expander = {
|
|
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
|
|
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
|
|
let i2c1 = device.I2C1.i2c(
|
|
(scl, sda),
|
|
400.khz(),
|
|
ccdr.peripheral.I2C1,
|
|
&ccdr.clocks,
|
|
);
|
|
mcp23017::MCP23017::default(i2c1).unwrap()
|
|
};
|
|
|
|
let spi = {
|
|
let spi_mosi = gpiod
|
|
.pd7
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_miso = gpioa
|
|
.pa6
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let spi_sck = gpiog
|
|
.pg11
|
|
.into_alternate_af5()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
});
|
|
|
|
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
|
|
// line causing a long RC decay.
|
|
device.SPI1.spi(
|
|
(spi_sck, spi_miso, spi_mosi),
|
|
config,
|
|
5.mhz(),
|
|
ccdr.peripheral.SPI1,
|
|
&ccdr.clocks,
|
|
)
|
|
};
|
|
|
|
let (adc1, adc2) = {
|
|
let (mut adc1, mut adc2) = hal::adc::adc12(
|
|
device.ADC1,
|
|
device.ADC2,
|
|
&mut delay,
|
|
ccdr.peripheral.ADC12,
|
|
&ccdr.clocks,
|
|
);
|
|
|
|
let adc1 = {
|
|
adc1.calibrate();
|
|
adc1.enable()
|
|
};
|
|
|
|
let adc2 = {
|
|
adc2.calibrate();
|
|
adc2.enable()
|
|
};
|
|
|
|
(adc1, adc2)
|
|
};
|
|
|
|
let adc1_in_p = gpiof.pf11.into_analog();
|
|
let adc2_in_p = gpiof.pf14.into_analog();
|
|
|
|
let pounder_devices = pounder::PounderDevices::new(
|
|
io_expander,
|
|
spi,
|
|
adc1,
|
|
adc2,
|
|
adc1_in_p,
|
|
adc2_in_p,
|
|
)
|
|
.unwrap();
|
|
|
|
let ad9959 = {
|
|
let qspi_interface = {
|
|
// Instantiate the QUADSPI pins and peripheral interface.
|
|
let qspi_pins = {
|
|
let _qspi_ncs = gpioc
|
|
.pc11
|
|
.into_alternate_af9()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let clk = gpiob
|
|
.pb2
|
|
.into_alternate_af9()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io0 = gpioe
|
|
.pe7
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io1 = gpioe
|
|
.pe8
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io2 = gpioe
|
|
.pe9
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
let io3 = gpioe
|
|
.pe10
|
|
.into_alternate_af10()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
(clk, io0, io1, io2, io3)
|
|
};
|
|
|
|
let qspi = hal::qspi::Qspi::bank2(
|
|
device.QUADSPI,
|
|
qspi_pins,
|
|
design_parameters::POUNDER_QSPI_FREQUENCY,
|
|
&ccdr.clocks,
|
|
ccdr.peripheral.QSPI,
|
|
);
|
|
|
|
pounder::QspiInterface::new(qspi).unwrap()
|
|
};
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
let reset_pin = gpiog.pg6.into_push_pull_output();
|
|
#[cfg(not(feature = "pounder_v1_1"))]
|
|
let reset_pin = gpioa.pa0.into_push_pull_output();
|
|
|
|
let mut io_update = gpiog.pg7.into_push_pull_output();
|
|
|
|
let ref_clk: hal::time::Hertz =
|
|
design_parameters::DDS_REF_CLK.into();
|
|
|
|
let mut ad9959 = ad9959::Ad9959::new(
|
|
qspi_interface,
|
|
reset_pin,
|
|
&mut io_update,
|
|
&mut delay,
|
|
ad9959::Mode::FourBitSerial,
|
|
ref_clk.0 as f32,
|
|
design_parameters::DDS_MULTIPLIER,
|
|
)
|
|
.unwrap();
|
|
|
|
ad9959.self_test().unwrap();
|
|
|
|
// Return IO_Update
|
|
gpiog.pg7 = io_update.into_analog();
|
|
|
|
ad9959
|
|
};
|
|
|
|
let dds_output = {
|
|
let io_update_trigger = {
|
|
let _io_update = gpiog
|
|
.pg7
|
|
.into_alternate_af2()
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
// Configure the IO_Update signal for the DDS.
|
|
let mut hrtimer = pounder::hrtimer::HighResTimerE::new(
|
|
device.HRTIM_TIME,
|
|
device.HRTIM_MASTER,
|
|
device.HRTIM_COMMON,
|
|
ccdr.clocks,
|
|
ccdr.peripheral.HRTIM,
|
|
);
|
|
|
|
// IO_Update occurs after a fixed delay from the QSPI write. Note that the timer
|
|
// is triggered after the QSPI write, which can take approximately 120nS, so
|
|
// there is additional margin.
|
|
hrtimer.configure_single_shot(
|
|
pounder::hrtimer::Channel::Two,
|
|
design_parameters::POUNDER_IO_UPDATE_DURATION,
|
|
design_parameters::POUNDER_IO_UPDATE_DELAY,
|
|
);
|
|
|
|
// Ensure that we have enough time for an IO-update every sample.
|
|
let sample_frequency = {
|
|
let timer_frequency: hal::time::Hertz =
|
|
design_parameters::TIMER_FREQUENCY.into();
|
|
timer_frequency.0 as f32 / sample_ticks as f32
|
|
};
|
|
|
|
let sample_period = 1.0 / sample_frequency;
|
|
assert!(
|
|
sample_period > design_parameters::POUNDER_IO_UPDATE_DELAY
|
|
);
|
|
|
|
hrtimer
|
|
};
|
|
|
|
let (qspi, config) = ad9959.freeze();
|
|
DdsOutput::new(qspi, io_update_trigger, config)
|
|
};
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
let pounder_stamper = {
|
|
log::info!("Assuming Pounder v1.1 or later");
|
|
let etr_pin = gpioa.pa0.into_alternate_af3();
|
|
|
|
// The frequency in the constructor is dont-care, as we will modify the period + clock
|
|
// source manually below.
|
|
let tim8 =
|
|
device
|
|
.TIM8
|
|
.timer(1.khz(), ccdr.peripheral.TIM8, &ccdr.clocks);
|
|
let mut timestamp_timer = timers::PounderTimestampTimer::new(tim8);
|
|
|
|
// Pounder is configured to generate a 500MHz reference clock, so a 125MHz sync-clock is
|
|
// output. As a result, dividing the 125MHz sync-clk provides a 31.25MHz tick rate for
|
|
// the timestamp timer. 31.25MHz corresponds with a 32ns tick rate.
|
|
// This is less than fCK_INT/3 of the timer as required for oversampling the trigger.
|
|
timestamp_timer.set_external_clock(timers::Prescaler::Div4);
|
|
timestamp_timer.start();
|
|
|
|
// Set the timer to wrap at the u16 boundary to meet the PLL periodicity.
|
|
// Scale and wrap before or after the PLL.
|
|
timestamp_timer.set_period_ticks(u16::MAX);
|
|
let tim8_channels = timestamp_timer.channels();
|
|
|
|
pounder::timestamp::Timestamper::new(
|
|
timestamp_timer,
|
|
tim8_channels.ch1,
|
|
&mut sampling_timer,
|
|
etr_pin,
|
|
batch_size,
|
|
)
|
|
};
|
|
|
|
Some(PounderDevices {
|
|
pounder: pounder_devices,
|
|
dds_output,
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
timestamper: pounder_stamper,
|
|
})
|
|
} else {
|
|
None
|
|
};
|
|
|
|
let cycle_counter = {
|
|
// Set TRCENA bit, which is required for DWT counter to tick. (This is also
|
|
// set automatically when running in the debugger, and only cleared on power
|
|
// reset, not on soft reset.)
|
|
core.DCB.enable_trace();
|
|
CycleCounter::new(core.DWT, ccdr.clocks.c_ck())
|
|
};
|
|
|
|
let stabilizer = StabilizerDevices {
|
|
afes,
|
|
adcs,
|
|
dacs,
|
|
timestamper: input_stamper,
|
|
net: network_devices,
|
|
adc_dac_timer: sampling_timer,
|
|
timestamp_timer,
|
|
cycle_counter,
|
|
digital_inputs,
|
|
};
|
|
|
|
// Enable the instruction cache.
|
|
core.SCB.enable_icache();
|
|
|
|
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
|
|
// info!("Built on {}", build_info::BUILT_TIME_UTC);
|
|
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
|
|
log::info!("setup() complete");
|
|
|
|
(stabilizer, pounder)
|
|
}
|