212 lines
10 KiB
Rust
212 lines
10 KiB
Rust
///! Stabilizer DAC management interface
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///!
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///! # Design
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///!
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///! Stabilizer DACs are connected to the MCU via a simplex, SPI-compatible interface. Each DAC
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///! accepts a 16-bit output code.
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///!
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///! In order to maximize CPU processing time, the DAC code updates are offloaded to hardware using
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///! a timer compare channel, DMA stream, and the DAC SPI interface.
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///!
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///! The timer comparison channel is configured to generate a DMA request whenever the comparison
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///! occurs. Thus, whenever a comparison happens, a single DAC code can be written to the output. By
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///! configuring a DMA stream for a number of successive DAC codes, hardware can regularly update
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///! the DAC without requiring the CPU.
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///!
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///! In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC
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///! output batch is always exactly 3 batches after the ADC batch that generated it.
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///!
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///! The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any
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///! transfer events generated by the timer (for example, when 2 update cycles occur before the DMA
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///! transfer completion is handled). In this mode, by the time DMA swaps buffers, there is always a valid buffer in the
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///! "next-transfer" double-buffer location for the DMA transfer. Once a transfer completes,
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///! software then has exactly one batch duration to fill the next buffer before its
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///! transfer begins. If software does not meet this deadline, old data will be repeatedly generated
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///! on the output and output will be shifted by one batch.
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///!
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///! ## Multiple Samples to Single DAC Codes
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///!
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///! For some applications, it may be desirable to generate a single DAC code from multiple ADC
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///! samples. In order to maintain timing characteristics between ADC samples and DAC code outputs,
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///! applications are required to generate one DAC code for each ADC sample. To accomodate mapping
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///! multiple inputs to a single output, the output code can be repeated a number of times in the
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///! output buffer corresponding with the number of input samples that were used to generate it.
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///!
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///!
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///! # Note
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///!
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///! There is a very small amount of latency between updating the two DACs due to bus matrix
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///! priority. As such, one of the DACs will be updated marginally earlier before the other because
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///! the DMA requests are generated simultaneously. This can be avoided by providing a known offset
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///! to other DMA requests, which can be completed by setting e.g. DAC0's comparison to a
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///! counter value of 2 and DAC1's comparison to a counter value of 3. This will have the effect of
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///! generating the DAC updates with a known latency of 1 timer tick to each other and prevent the
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///! DMAs from racing for the bus. As implemented, the DMA channels utilize natural priority of the
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///! DMA channels to arbitrate which transfer occurs first.
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///!
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///!
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///! # Limitations
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///!
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///! While double-buffered mode is used for DMA to avoid lost DAC-update events, there is no check
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///! for re-use of a previously provided DAC output buffer. It is assumed that the DMA request is
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///! served promptly after the transfer completes.
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use stm32h7xx_hal as hal;
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use crate::SAMPLE_BUFFER_SIZE;
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use super::timers;
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use hal::dma::{
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dma::{DMAReq, DmaConfig},
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traits::TargetAddress,
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MemoryToPeripheral, Transfer,
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};
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// The following global buffers are used for the DAC code DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being prepared while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined. The dimensions are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut DAC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 3]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 3]; 2];
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macro_rules! dac_output {
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($name:ident, $index:literal, $data_stream:ident,
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$spi:ident, $trigger_channel:ident, $dma_req:ident) => {
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/// $spi is used as a type for indicating a DMA transfer into the SPI TX FIFO
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struct $spi {
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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_channel: timers::tim2::$trigger_channel,
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}
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impl $spi {
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pub fn new(
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_channel: timers::tim2::$trigger_channel,
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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) -> Self {
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Self { _channel, spi }
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}
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/// Start the SPI and begin operating in a DMA-driven transfer mode.
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pub fn start_dma(&mut self) {
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// Allow the SPI FIFOs to operate using only DMA data channels.
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self.spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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self.spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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self.spi.inner().cr1.modify(|_, w| w.cstart().started());
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}
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}
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// Note(unsafe): This is safe because the DMA request line is logically owned by this module.
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// Additionally, the SPI is owned by this structure and is known to be configured for u16 word
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// sizes.
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unsafe impl TargetAddress<MemoryToPeripheral> for $spi {
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/// SPI is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI DMA requests are generated whenever TIM2 CHx ($dma_req) comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::$dma_req as u8);
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/// Whenever the DMA request occurs, it should write into SPI's TX FIFO.
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fn address(&self) -> usize {
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&self.spi.inner().txdr as *const _ as usize
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}
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}
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/// Represents data associated with DAC.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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// Note: SPI TX functionality may not be used from this structure to ensure safety with DMA.
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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$spi,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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}
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impl $name {
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/// Construct the DAC output channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `stream` - The DMA stream used to write DAC codes over SPI.
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/// * `trigger_channel` - The sampling timer output compare channel for update triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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trigger_channel: timers::tim2::$trigger_channel,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(4 + $index);
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// The stream constantly writes to the TX FIFO to write new update codes.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.double_buffer(true)
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.peripheral_increment(false);
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// Listen for any potential SPI error signals, which may indicate that we are not generating
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// update codes.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// AXISRAM is uninitialized. As such, we manually zero-initialize it here before
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// starting the transfer.
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// Note(unsafe): We currently own all DAC_BUF[index] buffers and are not using them
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// elsewhere, so it is safe to access them here.
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for buf in unsafe { DAC_BUF[$index].iter_mut() } {
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for byte in buf.iter_mut() {
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*byte = 0;
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}
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}
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// Construct the trigger stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> =
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Transfer::init(
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stream,
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$spi::new(trigger_channel, spi),
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// Note(unsafe): This buffer is only used once and provided for the DMA transfer.
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unsafe { &mut DAC_BUF[$index][0] },
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// Note(unsafe): This buffer is only used once and provided for the DMA transfer.
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unsafe { Some(&mut DAC_BUF[$index][1]) },
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trigger_config,
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);
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Self {
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transfer,
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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next_buffer: unsafe { Some(&mut DAC_BUF[$index][2]) },
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}
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}
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pub fn start(&mut self) {
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self.transfer.start(|spi| spi.start_dma());
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}
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/// Acquire the next output buffer to populate it with DAC codes.
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pub fn acquire_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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let next_buffer = self.next_buffer.take().unwrap();
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// Start the next transfer.
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_mut().unwrap()
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}
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}
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};
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}
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dac_output!(Dac0Output, 0, Stream6, SPI4, Channel3, TIM2_CH3);
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dac_output!(Dac1Output, 1, Stream7, SPI5, Channel4, TIM2_CH4);
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