396 lines
13 KiB
Rust
396 lines
13 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(asm)]
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// Enable returning `!`
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#![feature(never_type)]
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#[allow(unused_extern_crates)]
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#[cfg(not(feature = "semihosting"))]
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extern crate panic_abort;
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#[cfg(feature = "semihosting")]
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extern crate panic_semihosting;
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extern crate cortex_m;
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extern crate cortex_m_rt;
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extern crate stm32h7;
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#[macro_use]
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extern crate log;
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use core::ptr;
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use cortex_m_rt::{entry, exception};
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// use core::fmt::Write;
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use stm32h7::{stm32h7x3 as stm32};
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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#[cfg(feature = "semihosting")]
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fn init_log() {
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use log::LevelFilter;
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use cortex_m_log::log::{Logger, init};
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use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout};
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().expect("semihosting stdout"),
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level: LevelFilter::Info,
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};
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let logger = unsafe {
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LOGGER.get_or_insert(logger)
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};
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init(logger).expect("set logger");
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}
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// Pull in build information (from `built` crate)
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mod build_info {
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#![allow(dead_code)]
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include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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#[entry]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = stm32::Peripherals::take().unwrap();
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// go to VOS1 voltage scale high perf
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let pwr = dp.PWR;
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pwr.pwr_cr3.write(|w|
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w.sden().set_bit()
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.ldoen().set_bit()
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.bypass().clear_bit()
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);
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while pwr.pwr_csr1.read().actvosrdy().bit_is_clear() {}
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pwr.pwr_d3cr.write(|w| unsafe { w.vos().bits(0b11) }); // vos1
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while pwr.pwr_d3cr.read().vosrdy().bit_is_clear() {}
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let rcc = dp.RCC;
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// Reset all peripherals
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb1lrstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb1lrstr.write(|w| unsafe { w.bits(0)});
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rcc.apb1hrstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb1hrstr.write(|w| unsafe { w.bits(0)});
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rcc.ahb2rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb2rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb2rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb2rstr.write(|w| unsafe { w.bits(0)});
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// do not reset the cpu
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rcc.ahb3rstr.write(|w| unsafe { w.bits(0x7FFF_FFFF) });
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rcc.ahb3rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb3rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb3rstr.write(|w| unsafe { w.bits(0)});
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rcc.ahb4rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb4rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb4rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb4rstr.write(|w| unsafe { w.bits(0)});
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// Ensure HSI is on and stable
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rcc.cr.modify(|_, w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() {}
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// Set system clock to HSI
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi
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while rcc.cfgr.read().sws().bits() != 0 {}
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// Clear registers to reset value
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rcc.cr.write(|w| w.hsion().set_bit());
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rcc.cfgr.reset();
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// Ensure HSE is on and stable
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rcc.cr.modify(|_, w|
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w.hseon().set_bit()
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.hsebyp().clear_bit());
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while rcc.cr.read().hserdy().bit_is_clear() {}
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rcc.pllckselr.modify(|_, w| unsafe {
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w.pllsrc().bits(0b10) // hse
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.divm1().bits(1) // ref prescaler
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.divm2().bits(1) // ref prescaler
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});
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// Configure PLL1: 8MHz /1 *100 /2 = 400 MHz
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rcc.pllcfgr.modify(|_, w| unsafe {
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w.pll1vcosel().clear_bit() // 192-836 MHz VCO
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.pll1rge().bits(0b11) // 8-16 MHz PFD
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.pll1fracen().clear_bit()
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.divp1en().set_bit()
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.pll2vcosel().set_bit() // 150-420 MHz VCO
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.pll2rge().bits(0b11) // 8-16 MHz PFD
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.pll2fracen().clear_bit()
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.divp2en().set_bit()
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.divq2en().set_bit()
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});
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rcc.pll1divr.write(|w| unsafe {
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w.divn1().bits(100 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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});
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rcc.cr.modify(|_, w| w.pll1on().set_bit());
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while rcc.cr.read().pll1rdy().bit_is_clear() {}
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// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
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rcc.pll2divr.write(|w| unsafe {
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w.divn1().bits(25 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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.divq1().bits(2 - 1) // q output divider
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});
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rcc.cr.modify(|_, w| w.pll2on().set_bit());
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while rcc.cr.read().pll2rdy().bit_is_clear() {}
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// hclk 200 MHz, pclk 100 MHz
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let dapb = 0b100;
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rcc.d1cfgr.write(|w| unsafe {
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w.d1cpre().bits(0) // sys_ck not divided
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.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
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.d1ppre().bits(dapb) // rcc_pclk3 = rcc_hclk3 / 2
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});
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rcc.d2cfgr.write(|w| unsafe {
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w.d2ppre1().bits(dapb) // rcc_pclk1 = rcc_hclk3 / 2
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.d2ppre2().bits(dapb) // rcc_pclk2 = rcc_hclk3 / 2
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});
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rcc.d3cfgr.write(|w| unsafe {
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w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2
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});
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let flash = dp.FLASH;
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// 2 wait states, 0b10 programming delay
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// 185-210 MHz
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flash.acr.write(|w| unsafe {
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w.wrhighfreq().bits(2)
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.latency().bits(2)
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});
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while flash.acr.read().latency().bits() != 2 {}
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// Set system clock to pll1_p
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p
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while rcc.cfgr.read().sws().bits() != 0b011 {}
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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cp.DWT.enable_cycle_counter();
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// FP_LED0
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let gpiod = dp.GPIOD;
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rcc.ahb4enr.modify(|_, w| w.gpioden().set_bit());
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gpiod.otyper.modify(|_, w| w.ot5().push_pull());
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gpiod.moder.modify(|_, w| w.moder5().output());
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gpiod.odr.modify(|_, w| w.odr5().set_bit());
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// FP_LED1
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gpiod.otyper.modify(|_, w| w.ot6().push_pull());
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gpiod.moder.modify(|_, w| w.moder6().output());
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gpiod.odr.modify(|_, w| w.odr6().set_bit());
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// LED_FP2
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let gpiog = dp.GPIOG;
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rcc.ahb4enr.modify(|_, w| w.gpiogen().set_bit());
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gpiog.otyper.modify(|_, w| w.ot4().push_pull());
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gpiog.moder.modify(|_, w| w.moder4().output());
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gpiog.odr.modify(|_, w| w.odr4().set_bit());
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// LED_FP3
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gpiod.otyper.modify(|_, w| w.ot12().push_pull());
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gpiod.moder.modify(|_, w| w.moder12().output());
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gpiod.odr.modify(|_, w| w.odr12().set_bit());
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rcc.d1ccipr.write(|w| unsafe {
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w.ckpersrc().bits(1) // hse_ck
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});
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rcc.d2ccip1r.modify(|_, w| unsafe {
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w.spi123src().bits(1) // pll2_p
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.spi45src().bits(1) // pll2_q
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});
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rcc.d3ccipr.modify(|_, w| unsafe {
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w.spi6src().bits(1) // pll2_q
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});
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// Set up peripheral clocks
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rcc.ahb1enr.modify(|_, w|
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w.dma1en().set_bit()
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.dma2en().set_bit()
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);
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rcc.apb1lenr.modify(|_, w|
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w.spi2en().set_bit()
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.spi3en().set_bit()
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);
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rcc.apb2enr.modify(|_, w|
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w.spi1en().set_bit()
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.spi4en().set_bit()
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.spi5en().set_bit()
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);
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rcc.apb4enr.modify(|_, w|
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w.spi6en().set_bit()
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);
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let gpioa = dp.GPIOA;
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rcc.ahb4enr.modify(|_, w| w.gpioaen().set_bit());
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// AFE0_A0,1: PG2,PG3
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gpiog.otyper.modify(|_, w|
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w.ot2().push_pull()
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.ot3().push_pull()
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);
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gpiog.moder.modify(|_, w|
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w.moder2().output()
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.moder3().output()
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);
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gpiod.odr.modify(|_, w|
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w.odr2().clear_bit()
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.odr3().clear_bit()
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);
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// SCK: PG11
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gpiog.moder.modify(|_, w| w.moder11().alternate());
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gpiog.otyper.modify(|_, w| w.ot11().push_pull());
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gpiog.ospeedr.modify(|_, w| w.ospeedr11().very_high_speed());
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gpiog.afrh.modify(|_, w| w.afr11().af5());
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// MOSI: PD7
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// MISO: PA6
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gpioa.moder.modify(|_, w| w.moder6().alternate());
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gpioa.afrl.modify(|_, w| w.afr6().af5());
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// NSS: PG10
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gpiog.moder.modify(|_, w| w.moder10().alternate());
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gpiog.otyper.modify(|_, w| w.ot10().push_pull());
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gpiog.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiog.afrh.modify(|_, w| w.afr10().af5());
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let spi1 = dp.SPI1;
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spi1.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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spi1.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().set_bit()
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.cpha().set_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.ioswp().clear_bit()
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.midi().bits(2) // master inter data idle
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.mssi().bits(11) // master SS idle
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});
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spi1.cr2.modify(|_, w| unsafe {
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w.tsize().bits(1)
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});
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spi1.cr1.write(|w| w.spe().set_bit());
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let gpiob = dp.GPIOB;
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rcc.ahb4enr.modify(|_, w| w.gpioben().set_bit());
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// SCK: PB10
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gpiob.moder.modify(|_, w| w.moder10().alternate());
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gpiob.otyper.modify(|_, w| w.ot10().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr10().af5());
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// MOSI: PB15
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gpiob.moder.modify(|_, w| w.moder15().alternate());
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gpiob.otyper.modify(|_, w| w.ot15().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr15().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr15().af5());
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// MISO: PB14
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// NSS: PB9
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gpiob.moder.modify(|_, w| w.moder9().alternate());
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gpiob.otyper.modify(|_, w| w.ot9().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr9().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr9().af5());
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let gpioe = dp.GPIOE;
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rcc.ahb4enr.modify(|_, w| w.gpioeen().set_bit());
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// DAC0_LDAC: PE11
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gpioe.moder.modify(|_, w| w.moder11().output());
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gpioe.otyper.modify(|_, w| w.ot11().push_pull());
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gpioe.odr.modify(|_, w| w.odr11().clear_bit());
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// DAC_CLR: PE12
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gpioe.moder.modify(|_, w| w.moder12().output());
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gpioe.otyper.modify(|_, w| w.ot12().push_pull());
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gpioe.odr.modify(|_, w| w.odr12().set_bit());
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let spi2 = dp.SPI2;
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rcc.apb1lrstr.write(|w| w.spi2rst().set_bit());
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rcc.apb1lrstr.write(|w| w.spi2rst().clear_bit());
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rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit());
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spi2.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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spi2.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().clear_bit()
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.cpha().clear_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b01) // simplex transmitter
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.ioswp().clear_bit()
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.midi().bits(1) // master inter data idle
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.mssi().bits(0) // master SS idle
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});
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spi2.cr2.modify(|_, w| unsafe {
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w.tsize().bits(0) // infinite
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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loop {
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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// at least one SCK between EOT and CSTART
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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while spi1.sr.read().eot().bit_is_clear() {}
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spi1.ifcr.write(|w| w.eotc().set_bit());
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while spi1.sr.read().rxp().bit_is_clear() {}
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let a = spi1.rxdr.read().rxdr().bits() as i16;
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let d = (a as u16) ^ 0x8000;
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while spi2.sr.read().txp().bit_is_clear() {}
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let txdr = &spi2.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr, d) };
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while spi2.sr.read().txc().bit_is_clear() {}
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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info!("dac adc {:#x} cr1 {:#x} sr {:#x} cfg1 {:#x} cr2 {:#x}",
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a,
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spi2.cr1.read().bits(), spi2.sr.read().bits(),
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spi2.cfg1.read().bits(), spi2.cr2.read().bits(),
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);
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// cortex_m::asm::wfi();
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}
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}
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#[exception]
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fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
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panic!("HardFault at {:#?}", ef);
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}
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#[exception]
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fn DefaultHandler(irqn: i16) {
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panic!("Unhandled exception (IRQn = {})", irqn);
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}
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