156 lines
5.1 KiB
Rust
156 lines
5.1 KiB
Rust
#![deny(warnings)]
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#![no_std]
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#![no_main]
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use dsp::{lockin::Lockin, Accu};
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use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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use stabilizer::{hardware, hardware::design_parameters};
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// A constant sinusoid to send on the DAC output.
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// Full-scale gives a +/- 10V amplitude waveform. Scale it down to give +/- 1V.
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const ONE: i16 = (0.1 * u16::MAX as f32) as _;
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const SQRT2: i16 = (ONE as f32 * 0.707) as _;
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const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
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[ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2];
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adc: Adc1Input,
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dacs: (Dac0Output, Dac1Output),
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lockin: Lockin,
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
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// Enable ADC/DAC events
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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init::LateResources {
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lockin: Lockin::default(),
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afes: stabilizer.afes,
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adc: stabilizer.adcs.1,
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dacs: stabilizer.dacs,
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}
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}
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/// Main DSP processing routine for Stabilizer.
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///
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/// # Note
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/// Processing time for the DSP application code is bounded by the following constraints:
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///
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/// DSP application code starts after the ADC has generated a batch of samples and must be
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/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
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/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
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///
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/// The DSP application code must also fill out the next DAC output buffer in time such that the
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/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
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/// it's possible that old DAC codes will be generated on the output and the output samples will
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/// be delayed by 1 batch.
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///
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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///
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/// TODO: Document
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#[task(binds=DMA1_STR4, resources=[adc, dacs, lockin], priority=2)]
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fn process(c: process::Context) {
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let lockin = c.resources.lockin;
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let adc_samples = c.resources.adc.acquire_buffer();
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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// DAC0 always generates a fixed sinusoidal output.
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dac_samples[0]
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.iter_mut()
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.zip(DAC_SEQUENCE.iter())
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.for_each(|(d, s)| *d = *s as u16 ^ 0x8000);
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// Reference phase and frequency are known.
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let pll_phase = 0;
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let pll_frequency =
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2);
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// Harmonic index of the LO: -1 to _de_modulate the fundamental
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let harmonic: i32 = -1; // TODO: expose
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// Demodulation LO phase offset
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let phase_offset: i32 = (0.25 * i32::MAX as f32) as i32; // TODO: expose
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// Log2 lowpass time constant.
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let time_constant: u8 = 8;
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let sample_frequency = (pll_frequency as i32).wrapping_mul(harmonic);
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let sample_phase = phase_offset
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.wrapping_add((pll_phase as i32).wrapping_mul(harmonic));
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let output = adc_samples
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.iter()
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// Zip in the LO phase.
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.zip(Accu::new(sample_phase, sample_frequency))
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// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
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.map(|(&sample, phase)| {
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lockin.update(sample as i16, phase, time_constant)
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})
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// Decimate
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.last()
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.unwrap();
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for value in dac_samples[1].iter_mut() {
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*value = (output.arg() >> 16) as u16 ^ 0x8000;
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}
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}
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#[idle(resources=[afes])]
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fn idle(_: idle::Context) -> ! {
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loop {
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// TODO: Implement network interface.
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cortex_m::asm::wfi();
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}
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}
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { stm32h7xx_hal::ethernet::interrupt_handler() }
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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panic!("ADC1 input overrun");
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 output error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 output error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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