280 lines
9.5 KiB
Rust
280 lines
9.5 KiB
Rust
///! Stabilizer DAC management interface
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///!
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///! The Stabilizer DAC utilize a DMA channel to generate output updates. A timer channel is
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in DAC update for both channels.
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, TargetAddress,
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Transfer, SAMPLE_BUFFER_SIZE,
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};
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// The following global buffers are used for the DAC code DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being prepared while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined.
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#[link_section = ".axisram.buffers"]
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static mut DAC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut DAC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut DAC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut DAC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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/// SPI4 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI4 TX FIFO
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struct SPI4 {}
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impl SPI4 {
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pub fn new() -> Self {
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Self {}
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}
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}
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI4 {
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/// SPI2 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI4 DMA requests are generated whenever TIM2 CH3 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH3 as u8);
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/// Whenever the DMA request occurs, it should write into SPI4's TX FIFO.
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fn address(&self) -> u32 {
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let regs = unsafe { &*hal::stm32::SPI4::ptr() };
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®s.txdr as *const _ as u32
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}
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}
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/// SPI5 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI5 TX FIFO
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struct SPI5 {}
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impl SPI5 {
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pub fn new() -> Self {
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Self {}
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}
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}
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI5 {
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/// SPI5 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI5 DMA requests are generated whenever TIM2 CH4 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH4 as u8);
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/// Whenever the DMA request occurs, it should write into SPI5's TX FIFO
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fn address(&self) -> u32 {
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let regs = unsafe { &*hal::stm32::SPI5::ptr() };
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®s.txdr as *const _ as u32
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}
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}
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/// Represents both DAC output channels.
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pub struct DacOutputs {
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dac0: Dac0Output,
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dac1: Dac1Output,
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}
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impl DacOutputs {
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/// Construct the DAC outputs.
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pub fn new(dac0: Dac0Output, dac1: Dac1Output) -> Self {
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Self { dac0, dac1 }
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}
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/// Enqueue the next DAC output codes for transmission.
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///
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/// # Args
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/// * `dac0_codes` - The output codes for DAC0 to enqueue.
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/// * `dac1_codes` - The output codes for DAC1 to enqueue.
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pub fn next_data(
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&mut self,
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dac0_codes: &[u16; SAMPLE_BUFFER_SIZE],
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dac1_codes: &[u16; SAMPLE_BUFFER_SIZE],
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) {
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self.dac0.next_data(dac0_codes);
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self.dac1.next_data(dac1_codes);
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}
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}
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/// Represents data associated with DAC0.
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pub struct Dac0Output {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Disabled, u16>,
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transfer: Transfer<
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hal::dma::dma::Stream4<hal::stm32::DMA1>,
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SPI4,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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first_transfer: bool,
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}
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impl Dac0Output {
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/// Construct the DAC0 output channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `stream` - The DMA stream used to write DAC codes over SPI.
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/// * `trigger_channel` - The sampling timer output compare channel for update triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::Stream4<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::Timer2Channel3,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The stream constantly writes to the TX FIFO to write new update codes.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.peripheral_increment(false);
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// Construct the trigger stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init(
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stream,
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SPI4::new(),
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unsafe { &mut DAC0_BUF0 },
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None,
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trigger_config,
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);
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// Listen for any potential SPI error signals, which may indicate that we are not generating
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// update codes.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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Self {
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transfer,
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next_buffer: unsafe { Some(&mut DAC0_BUF1) },
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_spi: spi,
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first_transfer: true,
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}
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}
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/// Schedule the next set of DAC update codes.
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///
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/// # Args
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/// * `data` - The next samples to enqueue for transmission.
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pub fn next_data(&mut self, data: &[u16; SAMPLE_BUFFER_SIZE]) {
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let next_buffer = self.next_buffer.take().unwrap();
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// Copy data into the next buffer
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next_buffer.copy_from_slice(data);
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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while self.transfer.get_transfer_complete_flag() == false {}
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}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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}
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}
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/// Represents the data output stream from DAC1.
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pub struct Dac1Output {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Disabled, u16>,
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transfer: Transfer<
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hal::dma::dma::Stream5<hal::stm32::DMA1>,
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SPI5,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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first_transfer: bool,
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}
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impl Dac1Output {
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/// Construct a new DAC1 output data stream.
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///
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/// # Args
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/// * `spi` - The SPI interface connected to DAC1.
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/// * `stream` - The DMA stream used to write DAC codes the SPI TX FIFO.
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/// * `trigger_channel` - The timer channel used to generate DMA requests for DAC updates.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::Stream5<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::Timer2Channel4,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The trigger stream constantly writes to the TX FIFO to generate DAC updates.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.peripheral_increment(false)
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.circular_buffer(true);
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// Construct the stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init(
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stream,
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SPI5::new(),
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unsafe { &mut DAC1_BUF0 },
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None,
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trigger_config,
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);
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// Listen for any SPI errors, as this may indicate that we are not generating updates on the
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// DAC.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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Self {
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next_buffer: unsafe { Some(&mut DAC1_BUF1) },
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transfer,
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_spi: spi,
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first_transfer: true,
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}
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}
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/// Enqueue the next buffer for transmission to the DAC.
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///
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/// # Args
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/// * `data` - The next data to write to the DAC.
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pub fn next_data(&mut self, data: &[u16; SAMPLE_BUFFER_SIZE]) {
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let next_buffer = self.next_buffer.take().unwrap();
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// Copy data into the next buffer
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next_buffer.copy_from_slice(data);
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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while self.transfer.get_transfer_complete_flag() == false {}
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}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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}
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}
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