705 lines
23 KiB
Rust
705 lines
23 KiB
Rust
#![deny(warnings)]
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#![allow(clippy::missing_safety_doc)]
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#![no_std]
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#![no_main]
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#![cfg_attr(feature = "nightly", feature(asm))]
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// Enable returning `!`
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#![cfg_attr(feature = "nightly", feature(never_type))]
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#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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#[inline(never)]
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#[panic_handler]
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#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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let gpiod = unsafe { &*pac::GPIOD::ptr() };
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gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
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unsafe {
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core::intrinsics::abort();
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}
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}
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#[cfg(feature = "semihosting")]
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extern crate panic_semihosting;
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#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
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extern crate panic_halt;
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#[macro_use]
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extern crate log;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use core::fmt::Write;
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use cortex_m_rt::exception;
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use heapless::{consts::*, String, Vec};
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use rtfm::cyccnt::{Instant, U32Ext as _};
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::{
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prelude::*,
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stm32 as pac,
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};
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use embedded_hal::{
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digital::v2::OutputPin,
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};
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use smoltcp as net;
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use serde::{de::DeserializeOwned, Deserialize, Serialize};
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use serde_json_core::{de::from_slice, ser::to_string};
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mod eth;
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mod iir;
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use iir::*;
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mod board;
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mod eeprom;
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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#[cfg(feature = "semihosting")]
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fn init_log() {
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use cortex_m_log::log::{init as init_log, Logger};
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use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
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};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
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// Pull in build information (from `built` crate)
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mod build_info {
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#![allow(dead_code)]
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// include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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macro_rules! create_socket {
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($set:ident, $rx_storage:ident, $tx_storage:ident, $target:ident) => {
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let mut $rx_storage = [0; TCP_RX_BUFFER_SIZE];
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let mut $tx_storage = [0; TCP_TX_BUFFER_SIZE];
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let tcp_rx_buffer =
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net::socket::TcpSocketBuffer::new(&mut $rx_storage[..]);
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let tcp_tx_buffer =
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net::socket::TcpSocketBuffer::new(&mut $tx_storage[..]);
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let tcp_socket =
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net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
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let $target = $set.add(tcp_socket);
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};
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}
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type Adc1Spi = hal::spi::Spi<
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hal::stm32::SPI2,
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(
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hal::gpio::gpiob::PB10<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpiob::PB14<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpiob::PB9<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type Adc2Spi = hal::spi::Spi<
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hal::stm32::SPI3,
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(
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hal::gpio::gpioc::PC10<hal::gpio::Alternate<hal::gpio::AF6>>,
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hal::gpio::gpiob::PB4<hal::gpio::Alternate<hal::gpio::AF6>>,
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hal::spi::NoMosi,
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//hal::gpio::gpioa::PA15<hal::gpio::Alternate<hal::gpio::AF6>>,
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)
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>;
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type Dac1Spi = hal::spi::Spi<
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hal::stm32::SPI4,
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(
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hal::gpio::gpioe::PE2<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpioe::PE5<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpioe::PE4<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type Dac2Spi = hal::spi::Spi<
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hal::stm32::SPI5,
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(
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hal::gpio::gpiof::PF7<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::gpio::gpiof::PF8<hal::gpio::Alternate<hal::gpio::AF5>>,
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hal::spi::NoMosi,
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//hal::gpio::gpiof::PF6<hal::gpio::Alternate<hal::gpio::AF5>>,
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)
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>;
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type EepromI2c = hal::i2c::I2c<
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hal::stm32::I2C2,
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(
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hal::gpio::gpiof::PF1<hal::gpio::Alternate<hal::gpio::AF4>>,
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hal::gpio::gpiof::PF0<hal::gpio::Alternate<hal::gpio::AF4>>,
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)
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>;
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static DAT: u32 = 0x30; // EN | CSTART
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#[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc1: Adc1Spi,
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dac1: Dac1Spi,
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adc2: Adc2Spi,
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dac2: Dac2Spi,
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i2c: EepromI2c,
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// TODO: Add in pounder hardware resources.
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ethernet_periph:
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(pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL),
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#[init([[0.; 5]; 2])]
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iir_state: [IIRState; 2],
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#[init([IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
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iir_ch: [IIR; 2],
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#[link_section = ".sram3.eth"]
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#[init(eth::Device::new())]
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ethernet: eth::Device,
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}
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#[init(schedule = [tick])]
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fn init(c: init::Context) -> init::LateResources {
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let dp = c.device;
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let mut clocks = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let gpioa = dp.GPIOA.split(&mut clocks.ahb4);
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let gpiob = dp.GPIOB.split(&mut clocks.ahb4);
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let gpioc = dp.GPIOC.split(&mut clocks.ahb4);
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let gpiod = dp.GPIOD.split(&mut clocks.ahb4);
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let gpioe = dp.GPIOE.split(&mut clocks.ahb4);
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let gpiof = dp.GPIOF.split(&mut clocks.ahb4);
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let gpiog = dp.GPIOG.split(&mut clocks.ahb4);
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc1_spi = {
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let spi_miso = gpiob.pb14.into_alternate_af5();
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let spi_sck = gpiob.pb10.into_alternate_af5();
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let _spi_nss = gpiob.pb9.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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.cs_delay(220e-9)
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.frame_size(16)
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.freeze();
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let spi = hal::spi::Spi::spi2(
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dp.SPI2,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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//spi.listen(hal::spi::Event::Rxp);
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spi
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};
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let adc2_spi = {
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let spi_miso = gpiob.pb4.into_alternate_af6();
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let spi_sck = gpioc.pc10.into_alternate_af6();
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let _spi_nss = gpioa.pa15.into_alternate_af6();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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.frame_size(16)
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.cs_delay(220e-9)
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.freeze();
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let spi = hal::spi::Spi::spi3(
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dp.SPI3,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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//spi.listen(hal::spi::Event::Rxp);
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spi
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};
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let dac1_spi = {
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let spi_miso = gpioe.pe5.into_alternate_af5();
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let spi_sck = gpioe.pe2.into_alternate_af5();
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let _spi_nss = gpioe.pe4.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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.frame_size(16)
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.swap_mosi_miso()
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.freeze();
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let spi = hal::spi::Spi::spi4(
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dp.SPI4,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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spi
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};
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let dac2_spi = {
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let spi_miso = gpiof.pf8.into_alternate_af5();
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let spi_sck = gpiof.pf7.into_alternate_af5();
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let _spi_nss = gpiof.pf6.into_alternate_af5();
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let config = hal::spi::Config::new()
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.set_mode(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition})
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.frame_size(16)
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.swap_mosi_miso()
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.freeze();
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let spi = hal::spi::Spi::spi5(
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dp.SPI5,
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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&clocks);
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spi
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};
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// TODO: Configure the DMA
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//let mut dma = Dma::new(dp.DMA1, dp.DMAMUX1);
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//dma.configure_transfer(DmaTransfer::MemoryToPeripheral, DmaSource::Timer2, trigger_word,
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// &adc1_spi.spi.ptr().cr1.register)
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//dma.configure_transfer(DmaTransfer::MemoryToPeripheral, DmaSource::Timer2, trigger_word,
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// &adc2_spi.spi.ptr().cr1.register)
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// TODO: Configure timer 2 to trigger conversions for the ADC
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let _timer2 = hal::timer::Timer::tim2(dp.TIM2, 500.khz(), &mut clocks);
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cortex_m::asm::dsb();
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let dat_addr = &DAT as *const _ as usize;
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cp.SCB.clean_dcache_by_address(dat_addr, 4);
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board::dma1_setup(
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&dp.DMA1,
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&dp.DMAMUX1,
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dat_addr,
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&adc1_spi.spi.cr1 as *const _ as usize,
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&adc2_spi.spi.cr1 as *const _ as usize,
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);
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//timer2.enable_event(hal::timer::Event::DmaTransfer);
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// TODO: Configure the ethernet controller
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// Instantiate the QUADSPI pins and peripheral interface.
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// TODO: Place these into a pins structure that is provided to the QSPI constructor.
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let _qspi_clk = gpiob.pb2.into_alternate_af9();
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let _qspi_ncs = gpioc.pc11.into_alternate_af9();
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let _qspi_io0 = gpioe.pe7.into_alternate_af10();
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let _qspi_io1 = gpioe.pe8.into_alternate_af10();
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let _qspi_io2 = gpioe.pe9.into_alternate_af10();
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let _qspi_io3 = gpioe.pe10.into_alternate_af10();
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let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
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let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
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let mut fp_led_2 = gpiod.pd12.into_push_pull_output();
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let mut fp_led_3 = gpiog.pg4.into_push_pull_output();
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fp_led_0.set_low().unwrap();
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fp_led_1.set_low().unwrap();
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fp_led_2.set_low().unwrap();
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fp_led_3.set_low().unwrap();
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let _i2c1 = {
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let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
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let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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hal::i2c::I2c::i2c1(dp.I2C1, (scl, sda), 100.khz(), &clocks)
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};
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let i2c2 = {
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let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
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let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
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hal::i2c::I2c::i2c2(dp.I2C2, (scl, sda), 100.khz(), &clocks)
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};
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// Configure ethernet pins.
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let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_tx_en = gpiob.pb11.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_txd0 = gpiob.pb12.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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// TODO: This configuration seems to cause a system reset?
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//let _rmii_txd1 = gpiog.pg14.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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// Enable the ethernet peripheral.
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clocks.apb4.enr().modify(|_, w| w.syscfgen().set_bit());
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clocks.ahb1.enr().modify(|_, w| {
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w.eth1macen().set_bit()
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.eth1txen().set_bit()
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.eth1rxen().set_bit()
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});
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dp.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) }); // RMII
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cp.SCB.enable_icache();
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// The cycle counter is used for RTFM scheduling.
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cp.DWT.enable_cycle_counter();
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// c.schedule.tick(Instant::now()).unwrap();
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init::LateResources {
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adc1: adc1_spi,
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dac1: dac1_spi,
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adc2: adc2_spi,
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dac2: dac2_spi,
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i2c: i2c2,
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ethernet_periph: (
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dp.ETHERNET_MAC,
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dp.ETHERNET_DMA,
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dp.ETHERNET_MTL,
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),
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}
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}
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#[idle(resources = [ethernet, ethernet_periph, iir_state, iir_ch, i2c])]
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fn idle(c: idle::Context) -> ! {
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let (MAC, DMA, MTL) = c.resources.ethernet_periph;
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let hardware_addr = match eeprom::read_eui48(c.resources.i2c) {
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Err(_) => {
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info!("Could not read EEPROM, using default MAC address");
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net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
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}
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Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
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};
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info!("MAC: {}", hardware_addr);
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unsafe { c.resources.ethernet.init(hardware_addr, MAC, DMA, MTL) };
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let mut neighbor_cache_storage = [None; 8];
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let neighbor_cache =
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net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]);
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let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99);
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let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)];
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let mut iface =
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net::iface::EthernetInterfaceBuilder::new(c.resources.ethernet)
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.ethernet_addr(hardware_addr)
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.neighbor_cache(neighbor_cache)
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.ip_addrs(&mut ip_addrs[..])
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.finalize();
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let mut socket_set_entries: [_; 8] = Default::default();
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let mut sockets =
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net::socket::SocketSet::new(&mut socket_set_entries[..]);
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create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0);
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create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1);
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// unsafe { eth::enable_interrupt(DMA); }
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|
let mut time = 0u32;
|
|
let mut next_ms = Instant::now();
|
|
next_ms += 400_000.cycles();
|
|
let mut server = Server::new();
|
|
let mut iir_state: resources::iir_state = c.resources.iir_state;
|
|
let mut iir_ch: resources::iir_ch = c.resources.iir_ch;
|
|
loop {
|
|
// if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { }
|
|
let tick = Instant::now() > next_ms;
|
|
if tick {
|
|
next_ms += 400_000.cycles();
|
|
time += 1;
|
|
}
|
|
{
|
|
let socket =
|
|
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1234)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else if tick && socket.can_send() {
|
|
let s = iir_state.lock(|iir_state| Status {
|
|
t: time,
|
|
x0: iir_state[0][0],
|
|
y0: iir_state[0][2],
|
|
x1: iir_state[1][0],
|
|
y1: iir_state[1][2],
|
|
});
|
|
json_reply(socket, &s);
|
|
}
|
|
}
|
|
{
|
|
let socket =
|
|
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle1);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1235)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else {
|
|
server.poll(socket, |req: &Request| {
|
|
if req.channel < 2 {
|
|
iir_ch.lock(|iir_ch| {
|
|
iir_ch[req.channel as usize] = req.iir
|
|
});
|
|
}
|
|
});
|
|
}
|
|
}
|
|
|
|
if !match iface.poll(
|
|
&mut sockets,
|
|
net::time::Instant::from_millis(time as i64),
|
|
) {
|
|
Ok(changed) => changed,
|
|
Err(net::Error::Unrecognized) => true,
|
|
Err(e) => {
|
|
info!("iface poll error: {:?}", e);
|
|
true
|
|
}
|
|
} {
|
|
// cortex_m::asm::wfi();
|
|
}
|
|
}
|
|
}
|
|
|
|
#[task(priority = 1, schedule = [tick])]
|
|
fn tick(c: tick::Context) {
|
|
static mut TIME: u32 = 0;
|
|
*TIME += 1;
|
|
const PERIOD: u32 = 200_000_000;
|
|
c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap();
|
|
}
|
|
|
|
// seems to slow it down
|
|
// #[link_section = ".data.spi1"]
|
|
#[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
|
|
fn spi2(c: spi2::Context) {
|
|
#[cfg(feature = "bkpt")]
|
|
cortex_m::asm::bkpt();
|
|
let adc = c.resources.adc1;
|
|
let dac = c.resources.dac1;
|
|
let iir_ch = c.resources.iir_ch;
|
|
let iir_state = c.resources.iir_state;
|
|
|
|
// TODO: Doesn't make sense if RXP is unset.
|
|
if adc.is_rxp() {
|
|
let a: u16 = adc.read().unwrap();
|
|
|
|
let x0 = f32::from(a as i16);
|
|
let y0 = iir_ch[0].update(&mut iir_state[0], x0);
|
|
let d = y0 as i16 as u16 ^ 0x8000;
|
|
|
|
// TODO: Handle errors.
|
|
dac.send(d).unwrap();
|
|
}
|
|
#[cfg(feature = "bkpt")]
|
|
cortex_m::asm::bkpt();
|
|
}
|
|
|
|
#[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch], priority = 2)]
|
|
fn spi3(c: spi3::Context) {
|
|
#[cfg(feature = "bkpt")]
|
|
cortex_m::asm::bkpt();
|
|
let adc = c.resources.adc2;
|
|
let dac = c.resources.dac2;
|
|
let iir_ch = c.resources.iir_ch;
|
|
let iir_state = c.resources.iir_state;
|
|
|
|
// TODO: Doesn't make sense if RXP is unset.
|
|
if adc.is_rxp() {
|
|
let a: u16 = adc.read().unwrap();
|
|
|
|
let x0 = f32::from(a as i16);
|
|
let y0 = iir_ch[1].update(&mut iir_state[1], x0);
|
|
let d = y0 as i16 as u16 ^ 0x8000;
|
|
|
|
// TODO: Handle errors.
|
|
dac.send(d).unwrap();
|
|
}
|
|
#[cfg(feature = "bkpt")]
|
|
cortex_m::asm::bkpt();
|
|
}
|
|
|
|
/*
|
|
#[task(binds = ETH, resources = [ethernet_periph], priority = 1)]
|
|
fn eth(c: eth::Context) {
|
|
let dma = &c.resources.ethernet_periph.1;
|
|
ETHERNET_PENDING.store(true, Ordering::Relaxed);
|
|
unsafe { eth::interrupt_handler(dma) }
|
|
}
|
|
*/
|
|
|
|
extern "C" {
|
|
// hw interrupt handlers for RTFM to use for scheduling tasks
|
|
// one per priority
|
|
fn DCMI();
|
|
fn JPEG();
|
|
fn SDMMC();
|
|
}
|
|
};
|
|
|
|
#[derive(Deserialize, Serialize)]
|
|
struct Request {
|
|
channel: u8,
|
|
iir: IIR,
|
|
}
|
|
|
|
#[derive(Serialize)]
|
|
struct Response<'a> {
|
|
code: i32,
|
|
message: &'a str,
|
|
}
|
|
|
|
#[derive(Serialize)]
|
|
struct Status {
|
|
t: u32,
|
|
x0: f32,
|
|
y0: f32,
|
|
x1: f32,
|
|
y1: f32,
|
|
}
|
|
|
|
fn json_reply<T: Serialize>(socket: &mut net::socket::TcpSocket, msg: &T) {
|
|
let mut u: String<U128> = to_string(msg).unwrap();
|
|
u.push('\n').unwrap();
|
|
socket.write_str(&u).unwrap();
|
|
}
|
|
|
|
struct Server {
|
|
data: Vec<u8, U256>,
|
|
discard: bool,
|
|
}
|
|
|
|
impl Server {
|
|
fn new() -> Self {
|
|
Self {
|
|
data: Vec::new(),
|
|
discard: false,
|
|
}
|
|
}
|
|
|
|
fn poll<T, F, R>(
|
|
&mut self,
|
|
socket: &mut net::socket::TcpSocket,
|
|
f: F,
|
|
) -> Option<R>
|
|
where
|
|
T: DeserializeOwned,
|
|
F: FnOnce(&T) -> R,
|
|
{
|
|
while socket.can_recv() {
|
|
let found = socket
|
|
.recv(|buf| {
|
|
let (len, found) =
|
|
match buf.iter().position(|&c| c as char == '\n') {
|
|
Some(end) => (end + 1, true),
|
|
None => (buf.len(), false),
|
|
};
|
|
if self.data.len() + len >= self.data.capacity() {
|
|
self.discard = true;
|
|
self.data.clear();
|
|
} else if !self.discard && len > 0 {
|
|
self.data.extend_from_slice(&buf[..len]).unwrap();
|
|
}
|
|
(len, found)
|
|
})
|
|
.unwrap();
|
|
if found {
|
|
if self.discard {
|
|
self.discard = false;
|
|
json_reply(
|
|
socket,
|
|
&Response {
|
|
code: 520,
|
|
message: "command buffer overflow",
|
|
},
|
|
);
|
|
self.data.clear();
|
|
} else {
|
|
let r = from_slice::<T>(&self.data[..self.data.len() - 1]);
|
|
self.data.clear();
|
|
match r {
|
|
Ok(res) => {
|
|
let r = f(&res);
|
|
json_reply(
|
|
socket,
|
|
&Response {
|
|
code: 200,
|
|
message: "ok",
|
|
},
|
|
);
|
|
return Some(r);
|
|
}
|
|
Err(err) => {
|
|
warn!("parse error {:?}", err);
|
|
json_reply(
|
|
socket,
|
|
&Response {
|
|
code: 550,
|
|
message: "parse error",
|
|
},
|
|
);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
None
|
|
}
|
|
}
|
|
|
|
#[exception]
|
|
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
|
|
panic!("HardFault at {:#?}", ef);
|
|
}
|
|
|
|
#[exception]
|
|
fn DefaultHandler(irqn: i16) {
|
|
panic!("Unhandled exception (IRQn = {})", irqn);
|
|
}
|