385 lines
16 KiB
Rust
385 lines
16 KiB
Rust
///! Stabilizer ADC management interface
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///!
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///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured
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///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in an ADC sample read for both channels.
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///!
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///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is
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///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral,
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///! these DMA transfers stall when no data is available in the FIFO. Thus, the DMA transfer only
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///! completes after all samples have been read. When this occurs, a CPU interrupt is generated so
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///! that software can process the acquired samples from both ADCs. Only one of the ADC DMA streams
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///! is configured to generate an interrupt to handle both transfers, so it is necessary to ensure
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///! both transfers are completed before reading the data. This is usually not significant for
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///! busy-waiting because the transfers should complete at approximately the same time.
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral,
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PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE,
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};
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// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note
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// that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not
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// initialized on boot, so the contents are random.
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#[link_section = ".axisram.buffers"]
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static mut SPI_START: [u16; 1] = [0x00];
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// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined.
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#[link_section = ".axisram.buffers"]
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static mut ADC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut ADC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut ADC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut ADC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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/// SPI2 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI2 TX FIFO
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/// whenever the tim2 update dma request occurs.
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struct SPI2 {
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_channel: sampling_timer::tim2::Channel1,
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}
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impl SPI2 {
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pub fn new(_channel: sampling_timer::tim2::Channel1) -> Self {
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Self { _channel }
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}
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}
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// Note(unsafe): This structure is only safe to instantiate once. The DMA request is hard-coded and
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// may only be used if ownership of the timer2 channel 1 compare channel is assured, which is
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// ensured by maintaining ownership of the channel.
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI2 {
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/// SPI2 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI2 DMA requests are generated whenever TIM2 CH1 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH1 as u8);
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/// Whenever the DMA request occurs, it should write into SPI2's TX FIFO to start a DMA
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/// transfer.
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fn address(&self) -> u32 {
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// Note(unsafe): It is assumed that SPI2 is owned by another DMA transfer and this DMA is
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// only used for the transmit-half of DMA.
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let regs = unsafe { &*hal::stm32::SPI2::ptr() };
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®s.txdr as *const _ as u32
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}
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}
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/// SPI3 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI3 TX FIFO
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/// whenever the tim2 update dma request occurs.
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struct SPI3 {
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_channel: sampling_timer::tim2::Channel2,
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}
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impl SPI3 {
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pub fn new(_channel: sampling_timer::tim2::Channel2) -> Self {
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Self { _channel }
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}
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}
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// Note(unsafe): This structure is only safe to instantiate once. The DMA request is hard-coded and
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// may only be used if ownership of the timer2 channel 2 compare channel is assured, which is
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// ensured by maintaining ownership of the channel.
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI3 {
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/// SPI3 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI3 DMA requests are generated whenever TIM2 CH2 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH2 as u8);
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/// Whenever the DMA request occurs, it should write into SPI3's TX FIFO to start a DMA
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/// transfer.
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fn address(&self) -> u32 {
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// Note(unsafe): It is assumed that SPI3 is owned by another DMA transfer and this DMA is
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// only used for the transmit-half of DMA.
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let regs = unsafe { &*hal::stm32::SPI3::ptr() };
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®s.txdr as *const _ as u32
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}
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}
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/// Represents both ADC input channels.
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pub struct AdcInputs {
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adc0: Adc0Input,
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adc1: Adc1Input,
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}
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impl AdcInputs {
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/// Construct the ADC inputs.
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pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self {
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Self { adc0, adc1 }
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}
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/// Interrupt handler to handle when the sample collection DMA transfer completes.
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///
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/// # Returns
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/// (adc0, adc1) where adcN is a reference to the collected ADC samples. Two array references
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/// are returned - one for each ADC sample stream.
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pub fn transfer_complete_handler(
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&mut self,
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) -> (&[u16; SAMPLE_BUFFER_SIZE], &[u16; SAMPLE_BUFFER_SIZE]) {
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let adc0_buffer = self.adc0.transfer_complete_handler();
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let adc1_buffer = self.adc1.transfer_complete_handler();
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(adc0_buffer, adc1_buffer)
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}
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}
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/// Represents data associated with ADC0.
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pub struct Adc0Input {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::Stream1<hal::stm32::DMA1>,
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hal::spi::Spi<hal::stm32::SPI2, hal::spi::Disabled, u16>,
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PeripheralToMemory,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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_trigger_transfer: Transfer<
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hal::dma::dma::Stream0<hal::stm32::DMA1>,
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SPI2,
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MemoryToPeripheral,
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&'static mut [u16; 1],
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>,
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}
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impl Adc0Input {
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/// Construct the ADC0 input channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into
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/// the SPI TX FIFO.
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/// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer.
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/// * `_trigger_channel` - The ADC sampling timer output compare channel for read triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
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trigger_stream: hal::dma::dma::Stream0<hal::stm32::DMA1>,
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data_stream: hal::dma::dma::Stream1<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::Channel1,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The trigger stream constantly writes to the TX FIFO using a static word (dont-care
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// contents). Thus, neither the memory or peripheral address ever change. This is run in
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// circular mode to be completed at every DMA request.
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let trigger_config = DmaConfig::default()
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.priority(Priority::High)
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.circular_buffer(true);
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// Construct the trigger stream to write from memory to the peripheral.
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let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> =
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Transfer::init(
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trigger_stream,
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SPI2::new(trigger_channel),
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// Note(unsafe): Because this is a Memory->Peripheral transfer, this data is never
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// actually modified. It technically only needs to be immutably borrowed, but the
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// current HAL API only supports mutable borrows.
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unsafe { &mut SPI_START },
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None,
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trigger_config,
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);
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// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
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// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
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// after the requested number of samples have been collected. Note that only ADC1's data
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// stream is used to trigger a transfer completion interrupt.
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let data_config = DmaConfig::default()
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.memory_increment(true)
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.priority(Priority::VeryHigh);
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// A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This
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// indicates that samples were dropped due to excessive processing time in the main
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// application (e.g. a second DMA transfer completes before the first was done with
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// processing). This is used as a flow control indicator to guarantee that no ADC samples
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// are lost.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// The data transfer is always a transfer of data from the peripheral to a RAM buffer.
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let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> =
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Transfer::init(
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data_stream,
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spi,
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// Note(unsafe): The ADC0_BUF0 is "owned" by this peripheral. It shall not be used
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// anywhere else in the module.
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unsafe { &mut ADC0_BUF0 },
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None,
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data_config,
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);
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data_transfer.start(|spi| {
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_rx();
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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});
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trigger_transfer.start(|_| {});
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Self {
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// Note(unsafe): The ADC0_BUF1 is "owned" by this peripheral. It shall not be used
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// anywhere else in the module.
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next_buffer: unsafe { Some(&mut ADC0_BUF1) },
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transfer: data_transfer,
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_trigger_transfer: trigger_transfer,
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}
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}
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/// Handle a transfer completion.
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///
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/// # Returns
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/// A reference to the underlying buffer that has been filled with ADC samples.
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pub fn transfer_complete_handler(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] {
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let next_buffer = self.next_buffer.take().unwrap();
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// Wait for the transfer to fully complete before continuing.
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// Note: If a device hangs up, check that this conditional is passing correctly, as there is
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// no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_ref().unwrap()
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}
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}
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/// Represents the data input stream from ADC1
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pub struct Adc1Input {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::Stream3<hal::stm32::DMA1>,
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hal::spi::Spi<hal::stm32::SPI3, hal::spi::Disabled, u16>,
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PeripheralToMemory,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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_trigger_transfer: Transfer<
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hal::dma::dma::Stream2<hal::stm32::DMA1>,
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SPI3,
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MemoryToPeripheral,
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&'static mut [u16; 1],
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>,
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}
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impl Adc1Input {
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/// Construct a new ADC1 input data stream.
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///
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/// # Args
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/// * `spi` - The SPI interface connected to ADC1.
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/// * `trigger_stream` - The DMA stream used to trigger ADC conversions on the SPI interface.
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/// * `data_stream` - The DMA stream used to read ADC samples from the SPI RX FIFO.
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/// * `trigger_channel` - The ADC sampling timer output compare channel for read triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
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trigger_stream: hal::dma::dma::Stream2<hal::stm32::DMA1>,
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data_stream: hal::dma::dma::Stream3<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::Channel2,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The trigger stream constantly writes to the TX FIFO using a static word (dont-care
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// contents). Thus, neither the memory or peripheral address ever change. This is run in
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// circular mode to be completed at every DMA request.
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let trigger_config = DmaConfig::default()
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.priority(Priority::High)
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.circular_buffer(true);
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// Construct the trigger stream to write from memory to the peripheral.
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let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> =
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Transfer::init(
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trigger_stream,
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SPI3::new(trigger_channel),
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// Note(unsafe). This transaction is read-only and SPI_START is a dont-care value,
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// so it is always safe to share.
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unsafe { &mut SPI_START },
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None,
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trigger_config,
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);
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// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
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// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
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// after the requested number of samples have been collected. Note that only ADC1's data
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// stream is used to trigger a transfer completion interrupt.
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let data_config = DmaConfig::default()
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.memory_increment(true)
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.transfer_complete_interrupt(true)
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.priority(Priority::VeryHigh);
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// A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This
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// indicates that samples were dropped due to excessive processing time in the main
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// application (e.g. a second DMA transfer completes before the first was done with
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// processing). This is used as a flow control indicator to guarantee that no ADC samples
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// are lost.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// The data transfer is always a transfer of data from the peripheral to a RAM buffer.
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let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> =
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Transfer::init(
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data_stream,
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spi,
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// Note(unsafe): The ADC1_BUF0 is "owned" by this peripheral. It shall not be used
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// anywhere else in the module.
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unsafe { &mut ADC1_BUF0 },
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None,
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data_config,
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);
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data_transfer.start(|spi| {
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_rx();
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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});
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trigger_transfer.start(|_| {});
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Self {
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// Note(unsafe): The ADC1_BUF1 is "owned" by this peripheral. It shall not be used
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// anywhere else in the module.
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next_buffer: unsafe { Some(&mut ADC1_BUF1) },
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transfer: data_transfer,
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_trigger_transfer: trigger_transfer,
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}
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}
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/// Handle a transfer completion.
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///
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/// # Returns
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/// A reference to the underlying buffer that has been filled with ADC samples.
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pub fn transfer_complete_handler(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] {
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let next_buffer = self.next_buffer.take().unwrap();
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// Wait for the transfer to fully complete before continuing.
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// Note: If a device hangs up, check that this conditional is passing correctly, as there is
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// no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_ref().unwrap()
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}
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}
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