380 lines
15 KiB
Rust
380 lines
15 KiB
Rust
///! The sampling timer is used for managing ADC sampling and external reference timestamping.
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use super::hal;
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use hal::stm32::{
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// TIM1 and TIM8 have identical registers.
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tim1 as __tim8,
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tim2 as __tim2,
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// TIM2 and TIM5 have identical registers.
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tim2 as __tim5,
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tim3 as __tim3,
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};
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/// The event that should generate an external trigger from the peripheral.
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#[allow(dead_code)]
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pub enum TriggerGenerator {
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Reset = 0b000,
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Enable = 0b001,
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Update = 0b010,
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ComparePulse = 0b011,
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Ch1Compare = 0b100,
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Ch2Compare = 0b101,
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Ch3Compare = 0b110,
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Ch4Compare = 0b111,
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}
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/// Selects the trigger source for the timer peripheral.
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#[allow(dead_code)]
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pub enum TriggerSource {
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Trigger0 = 0,
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Trigger1 = 0b01,
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Trigger2 = 0b10,
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Trigger3 = 0b11,
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}
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/// Prescalers for externally-supplied reference clocks.
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#[allow(dead_code)]
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pub enum Prescaler {
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Div1 = 0b00,
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Div2 = 0b01,
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Div4 = 0b10,
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Div8 = 0b11,
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}
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/// Optional slave operation modes of a timer.
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#[allow(dead_code)]
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pub enum SlaveMode {
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Disabled = 0,
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Trigger = 0b0110,
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}
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/// Optional input capture preconditioning filter configurations.
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#[allow(dead_code)]
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pub enum InputFilter {
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Div1N1 = 0b0000,
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Div1N8 = 0b0011,
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}
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macro_rules! timer_channels {
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($name:ident, $TY:ident, $size:ty) => {
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paste::paste! {
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/// The timer used for managing ADC sampling.
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pub struct $name {
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timer: hal::timer::Timer<hal::stm32::[< $TY >]>,
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channels: Option<[< $TY:lower >]::Channels>,
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update_event: Option<[< $TY:lower >]::UpdateEvent>,
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}
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impl $name {
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/// Construct the sampling timer.
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#[allow(dead_code)]
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pub fn new(mut timer: hal::timer::Timer<hal::stm32::[< $TY>]>) -> Self {
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timer.pause();
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Self {
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timer,
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// Note(unsafe): Once these channels are taken, we guarantee that we do not
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// modify any of the underlying timer channel registers, as ownership of the
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// channels is now provided through the associated channel structures. We
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// additionally guarantee this can only be called once because there is only
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// one Timer2 and this resource takes ownership of it once instantiated.
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channels: unsafe { Some([< $TY:lower >]::Channels::new()) },
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update_event: unsafe { Some([< $TY:lower >]::UpdateEvent::new()) },
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}
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}
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/// Get the timer capture/compare channels.
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#[allow(dead_code)]
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pub fn channels(&mut self) -> [< $TY:lower >]::Channels {
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self.channels.take().unwrap()
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}
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/// Get the timer update event.
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#[allow(dead_code)]
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pub fn update_event(&mut self) -> [< $TY:lower >]::UpdateEvent {
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self.update_event.take().unwrap()
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}
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/// Get the period of the timer.
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#[allow(dead_code)]
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pub fn get_period(&self) -> $size {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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regs.arr.read().arr().bits()
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}
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/// Manually set the period of the timer.
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#[allow(dead_code)]
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pub fn set_period_ticks(&mut self, period: $size) {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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regs.arr.write(|w| w.arr().bits(period));
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// Force the new period to take effect immediately.
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self.timer.apply_freq();
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}
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/// Clock the timer from an external source.
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///
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/// # Note:
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/// * Currently, only an external source applied to ETR is supported.
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///
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/// # Args
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/// * `prescaler` - The prescaler to use for the external source.
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#[allow(dead_code)]
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pub fn set_external_clock(&mut self, prescaler: Prescaler) {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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regs.smcr.modify(|_, w| w.etps().bits(prescaler as u8).ece().set_bit());
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// Clear any other prescaler configuration.
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regs.psc.write(|w| w.psc().bits(0));
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}
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/// Start the timer.
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#[allow(dead_code)]
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pub fn start(&mut self) {
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// Force a refresh of the frequency settings.
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self.timer.apply_freq();
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self.timer.reset_counter();
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self.timer.resume();
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}
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/// Configure the timer peripheral to generate a trigger based on the provided
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/// source.
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#[allow(dead_code)]
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pub fn generate_trigger(&mut self, source: TriggerGenerator) {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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// Note(unsafe) The TriggerGenerator enumeration is specified such that this is
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// always in range.
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regs.cr2.modify(|_, w| w.mms().bits(source as u8));
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}
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/// Select a trigger source for the timer peripheral.
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#[allow(dead_code)]
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pub fn set_trigger_source(&mut self, source: TriggerSource) {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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// Note(unsafe) The TriggerSource enumeration is specified such that this is
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// always in range.
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regs.smcr.modify(|_, w| unsafe { w.ts().bits(source as u8) } );
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}
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#[allow(dead_code)]
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pub fn set_slave_mode(&mut self, source: TriggerSource, mode: SlaveMode) {
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let regs = unsafe { &*hal::stm32::$TY::ptr() };
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// Note(unsafe) The TriggerSource and SlaveMode enumerations are specified such
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// that they are always in range.
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regs.smcr.modify(|_, w| unsafe { w.sms().bits(mode as u8).ts().bits(source as u8) } );
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}
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}
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pub mod [< $TY:lower >] {
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use stm32h7xx_hal as hal;
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use hal::dma::{traits::TargetAddress, PeripheralToMemory, dma::DMAReq};
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use hal::stm32::$TY;
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pub struct UpdateEvent {}
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impl UpdateEvent {
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/// Create a new update event
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///
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/// Note(unsafe): This is only safe to call once.
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#[allow(dead_code)]
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pub unsafe fn new() -> Self {
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Self {}
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}
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/// Enable DMA requests upon timer updates.
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#[allow(dead_code)]
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pub fn listen_dma(&self) {
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// Note(unsafe): We perform only atomic operations on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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regs.dier.modify(|_, w| w.ude().set_bit());
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}
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/// Trigger a DMA request manually
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#[allow(dead_code)]
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pub fn trigger(&self) {
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let regs = unsafe { &*<$TY>::ptr() };
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regs.egr.write(|w| w.ug().set_bit());
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}
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}
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/// The channels representing the timer.
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pub struct Channels {
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pub ch1: Channel1,
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pub ch2: Channel2,
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pub ch3: Channel3,
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pub ch4: Channel4,
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}
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impl Channels {
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/// Construct a new set of channels.
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///
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/// Note(unsafe): This is only safe to call once.
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#[allow(dead_code)]
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pub unsafe fn new() -> Self {
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Self {
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ch1: Channel1::new(),
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ch2: Channel2::new(),
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ch3: Channel3::new(),
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ch4: Channel4::new(),
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}
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}
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}
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timer_channels!(1, $TY, ccmr1, $size);
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timer_channels!(2, $TY, ccmr1, $size);
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timer_channels!(3, $TY, ccmr2, $size);
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timer_channels!(4, $TY, ccmr2, $size);
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}
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}
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};
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($index:expr, $TY:ty, $ccmrx:expr, $size:ty) => {
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paste::paste! {
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pub use super::[< __ $TY:lower >]::[< $ccmrx _input >]::[< CC $index S_A>] as [< CaptureSource $index >];
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/// A capture/compare channel of the timer.
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pub struct [< Channel $index >] {}
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/// A capture channel of the timer.
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pub struct [< Channel $index InputCapture>] {}
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impl [< Channel $index >] {
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/// Construct a new timer channel.
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///
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/// Note(unsafe): This function must only be called once. Once constructed, the
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/// constructee guarantees to never modify the timer channel.
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#[allow(dead_code)]
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unsafe fn new() -> Self {
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Self {}
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}
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/// Allow the channel to generate DMA requests.
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#[allow(dead_code)]
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pub fn listen_dma(&self) {
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let regs = unsafe { &*<$TY>::ptr() };
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regs.dier.modify(|_, w| w.[< cc $index de >]().set_bit());
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}
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/// Operate the channel as an output-compare.
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///
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/// # Args
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/// * `value` - The value to compare the sampling timer's counter against.
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#[allow(dead_code)]
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pub fn to_output_compare(&self, value: $size) {
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let regs = unsafe { &*<$TY>::ptr() };
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let arr = regs.arr.read().bits() as $size;
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assert!(value <= arr);
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regs.[< ccr $index >].write(|w| w.ccr().bits(value));
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regs.[< $ccmrx _output >]()
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.modify(|_, w| unsafe { w.[< cc $index s >]().bits(0) });
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}
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/// Operate the channel in input-capture mode.
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///
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/// # Args
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/// * `input` - The input source for the input capture event.
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#[allow(dead_code)]
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pub fn into_input_capture(self, input: [< CaptureSource $index >]) -> [< Channel $index InputCapture >]{
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let regs = unsafe { &*<$TY>::ptr() };
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regs.[< $ccmrx _input >]().modify(|_, w| w.[< cc $index s>]().variant(input));
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[< Channel $index InputCapture >] {}
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}
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}
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impl [< Channel $index InputCapture >] {
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/// Get the latest capture from the channel.
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#[allow(dead_code)]
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pub fn latest_capture(&mut self) -> Result<Option<$size>, Option<$size>> {
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// Note(unsafe): This channel owns all access to the specific timer channel.
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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let result = if regs.sr.read().[< cc $index if >]().bit_is_set() {
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// Read the capture value. Reading the captured value clears the flag in the
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// status register automatically.
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Some(regs.[< ccr $index >].read().ccr().bits())
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} else {
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None
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};
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// Read SR again to check for a potential over-capture. If there is an
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// overcapture, return an error.
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if regs.sr.read().[< cc $index of >]().bit_is_set() {
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regs.sr.modify(|_, w| w.[< cc $index of >]().clear_bit());
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Err(result)
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} else {
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Ok(result)
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}
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}
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/// Allow the channel to generate DMA requests.
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#[allow(dead_code)]
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pub fn listen_dma(&self) {
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// Note(unsafe): This channel owns all access to the specific timer channel.
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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regs.dier.modify(|_, w| w.[< cc $index de >]().set_bit());
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}
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/// Enable the input capture to begin capturing timer values.
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#[allow(dead_code)]
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pub fn enable(&mut self) {
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// Read the latest input capture to clear any pending data in the register.
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let _ = self.latest_capture();
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// Note(unsafe): This channel owns all access to the specific timer channel.
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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regs.ccer.modify(|_, w| w.[< cc $index e >]().set_bit());
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}
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/// Check if an over-capture event has occurred.
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#[allow(dead_code)]
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pub fn check_overcapture(&self) -> bool {
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// Note(unsafe): This channel owns all access to the specific timer channel.
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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regs.sr.read().[< cc $index of >]().bit_is_set()
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}
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/// Configure the input capture input pre-filter.
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///
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/// # Args
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/// * `filter` - The desired input filter stage configuration. Defaults to disabled.
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#[allow(dead_code)]
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pub fn configure_filter(&mut self, filter: super::InputFilter) {
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// Note(unsafe): This channel owns all access to the specific timer channel.
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// Only atomic operations on completed on the timer registers.
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let regs = unsafe { &*<$TY>::ptr() };
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regs.[< $ccmrx _input >]().modify(|_, w| w.[< ic $index f >]().bits(filter as u8));
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}
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}
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// Note(unsafe): This manually implements DMA support for input-capture channels. This
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// is safe as it is only completed once per channel and each DMA request is allocated to
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// each channel as the owner.
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unsafe impl TargetAddress<PeripheralToMemory> for [< Channel $index InputCapture >] {
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type MemSize = $size;
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const REQUEST_LINE: Option<u8> = Some(DMAReq::[< $TY _CH $index >]as u8);
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fn address(&self) -> usize {
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let regs = unsafe { &*<$TY>::ptr() };
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®s.[<ccr $index >] as *const _ as usize
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}
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}
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}
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};
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}
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timer_channels!(SamplingTimer, TIM2, u32);
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timer_channels!(ShadowSamplingTimer, TIM3, u16);
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timer_channels!(TimestampTimer, TIM5, u32);
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timer_channels!(PounderTimestampTimer, TIM8, u16);
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