108 lines
3.5 KiB
Rust
108 lines
3.5 KiB
Rust
///! The DdsOutput is used as an output stream to the pounder DDS.
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use super::QspiInterface;
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use crate::hrtimer::HighResTimerE;
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use ad9959::{Channel, DdsConfig, ProfileSerializer};
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use stm32h7xx_hal as hal;
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/// The DDS profile update stream.
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pub struct DdsOutput {
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_qspi: QspiInterface,
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io_update_trigger: HighResTimerE,
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config: DdsConfig,
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}
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impl DdsOutput {
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/// Construct a new DDS output stream.
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///
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/// # Note
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/// It is assumed that the QSPI stream and the IO_Update trigger timer have been configured in a
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/// way such that the profile has sufficient time to be written before the IO_Update signal is
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/// generated.
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///
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/// # Args
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/// * `qspi` - The QSPI interface to the run the stream on.
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/// * `io_update_trigger` - The HighResTimerE used to generate IO_Update pulses.
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/// * `dds_config` - The frozen DDS configuration.
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pub fn new(
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mut qspi: QspiInterface,
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io_update_trigger: HighResTimerE,
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dds_config: DdsConfig,
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) -> Self {
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qspi.start_stream();
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Self {
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config: dds_config,
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_qspi,
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io_update_trigger,
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}
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}
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/// Get a builder for serializing a Pounder DDS profile.
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pub fn builder(&mut self) -> ProfileBuilder {
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let builder = self.config.builder();
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ProfileBuilder {
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dds_stream: self,
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serializer: builder,
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}
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}
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/// Write a profile to the stream.
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///
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/// # Note:
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/// If a profile of more than 4 words is provided, it is possible that the QSPI interface will
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/// stall execution.
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///
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/// # Args
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/// * `profile` - The serialized DDS profile to write.
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fn write_profile(&mut self, profile: &[u32]) {
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// Note(unsafe): We own the QSPI interface, so it is safe to access the registers in a raw
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// fashion.
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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for word in profile.iter() {
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// Note(unsafe): We are writing to the SPI TX FIFO in a raw manner for performance. This
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// is safe because we know the data register is a valid address to write to.
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unsafe {
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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*word,
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);
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}
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}
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// Trigger the IO_update signal generating timer to asynchronous create the IO_Update pulse.
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self.io_update_trigger.trigger();
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}
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}
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/// A temporary builder for serializing and writing profiles.
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pub struct ProfileBuilder<'a> {
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dds_stream: &'a mut DdsOutput,
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serializer: ProfileSerializer,
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}
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impl<'a> ProfileBuilder<'a> {
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/// Update a number of channels with the provided configuration
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///
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/// # Args
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/// * `channels` - A list of channels to apply the configuration to.
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/// * `ftw` - If provided, indicates a frequency tuning word for the channels.
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/// * `pow` - If provided, indicates a phase offset word for the channels.
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/// * `acr` - If provided, indicates the amplitude control register for the channels.
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pub fn update_channels(
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mut self,
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channels: &[Channel],
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ftw: Option<u32>,
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pow: Option<u16>,
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acr: Option<u16>,
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) -> Self {
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self.serializer.update_channels(channels, ftw, pow, acr);
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self
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}
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/// Write the profile to the DDS asynchronously.
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pub fn write_profile(mut self) {
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let profile = self.serializer.finalize();
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self.dds_stream.write_profile(profile);
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}
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}
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