406 lines
21 KiB
Rust
406 lines
21 KiB
Rust
///! Stabilizer ADC management interface
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///!
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///! # Design
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///!
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///! Stabilizer ADCs are connected to the MCU via a simplex, SPI-compatible interface. The ADCs
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///! require a setup conversion time after asserting the CSn (convert) signal to generate the ADC
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///! code from the sampled level. Once the setup time has elapsed, the ADC data is clocked out of
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///! MISO. The internal setup time is managed by the SPI peripheral via a CSn setup time parameter
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///! during SPI configuration, which allows offloading the management of the setup time to hardware.
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///!
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///! Because of the SPI-compatibility of the ADCs, a single SPI peripheral + DMA is used to automate
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///! the collection of multiple ADC samples without requiring processing by the CPU, which reduces
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///! overhead and provides the CPU with more time for processing-intensive tasks, like DSP.
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///!
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///! The automation of sample collection utilizes three DMA streams, the SPI peripheral, and two
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///! timer compare channel for each ADC. One timer comparison channel is configured to generate a
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///! comparison event every time the timer is equal to a specific value. Each comparison then
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///! generates a DMA transfer event to write into the SPI CR1 register to initiate the transfer.
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///! This allows the SPI interface to periodically read a single sample. The other timer comparison
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///! channel is configured to generate a comparison event slightly before the first (~10 timer
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///! cycles). This channel triggers a separate DMA stream to clear the EOT flag within the SPI
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///! peripheral. The EOT flag must be cleared after each transfer or the SPI peripheral will not
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///! properly complete the single conversion. Thus, by using two DMA streams and timer comparison
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///! channels, the SPI can regularly acquire ADC samples.
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///!
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///! In order to collect the acquired ADC samples into a RAM buffer, a final DMA transfer is
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///! configured to read from the SPI RX FIFO into RAM. The request for this transfer is connected to
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///! the SPI RX data signal, so the SPI peripheral will request to move data into RAM whenever it is
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///! available. When enough samples have been collected, a transfer-complete interrupt is generated
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///! and the ADC samples are available for processing.
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///!
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///! The SPI peripheral internally has an 8- or 16-byte TX and RX FIFO, which corresponds to a 4- or
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///! 8-sample buffer for incoming ADC samples. During the handling of the DMA transfer completion,
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///! there is a small window where buffers are swapped over where it's possible that a sample could
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///! be lost. In order to avoid this, the SPI RX FIFO is effectively used as a "sample overflow"
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///! region and can buffer a number of samples until the next DMA transfer is configured. If a DMA
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///! transfer is still not set in time, the SPI peripheral will generate an input-overrun interrupt.
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///! This interrupt then serves as a means of detecting if samples have been lost, which will occur
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///! whenever data processing takes longer than the collection period.
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///!
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///!
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///! ## Starting Data Collection
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///!
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///! Because the DMA data collection is automated via timer count comparisons and DMA transfers, the
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///! ADCs can be initialized and configured, but will not begin sampling the external ADCs until the
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///! sampling timer is enabled. As such, the sampling timer should be enabled after all
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///! initialization has completed and immediately before the embedded processing loop begins.
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///!
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///!
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///! ## Batch Sizing
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///!
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///! The ADCs collect a group of N samples, which is referred to as a batch. The size of the batch
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///! is configured by the user at compile-time to allow for a custom-tailored implementation. Larger
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///! batch sizes generally provide for lower overhead and more processing time per sample, but come
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///! at the expense of increased input -> output latency.
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///!
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///!
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///! # Note
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///!
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///! While there are two ADCs, only a single ADC is configured to generate transfer-complete
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///! interrupts. This is done because it is assumed that the ADCs will always be sampled
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///! simultaneously. If only a single ADC is used, it must always be ADC0, as ADC1 will not generate
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///! transfer-complete interrupts.
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///!
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///! There is a very small amount of latency between sampling of ADCs due to bus matrix priority. As
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///! such, one of the ADCs will be sampled marginally earlier before the other because the DMA
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///! requests are generated simultaneously. This can be avoided by providing a known offset to the
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///! sample DMA requests, which can be completed by setting e.g. ADC0's comparison to a counter
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///! value of 0 and ADC1's comparison to a counter value of 1.
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///!
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///! In this implementation, single buffer mode DMA transfers are used because the SPI RX FIFO can
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///! be used as a means to both detect and buffer ADC samples during the buffer swap-over. Because
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///! of this, double-buffered mode does not offer any advantages over single-buffered mode (unless
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///! double-buffered mode offers less overhead due to the DMA disable/enable procedure).
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use stm32h7xx_hal as hal;
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use super::design_parameters::SAMPLE_BUFFER_SIZE;
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use super::timers;
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use hal::dma::{
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config::Priority,
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dma::{DMAReq, DmaConfig},
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traits::TargetAddress,
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MemoryToPeripheral, PeripheralToMemory, Transfer,
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};
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/// A type representing an ADC sample.
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#[derive(Copy, Clone)]
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pub struct AdcCode(pub u16);
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impl Into<f32> for AdcCode {
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/// Convert raw ADC codes to/from voltage levels.
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///
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/// # Note
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///
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/// This does not account for the programmable gain amplifier at the signal input.
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fn into(self) -> f32 {
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// The input voltage is measured by the ADC across a dynamic scale of +/- 4.096 V with a
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// dynamic range across signed integers. Additionally, the signal is fully differential, so
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// the differential voltage is measured at the ADC. Thus, the single-ended signal is
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// measured at the input is half of the ADC-reported measurement. As a pre-filter, the
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// input signal has a fixed gain of 1/5 through a static input active filter.
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let adc_volts_per_lsb = 5.0 / 2.0 * 4.096 / i16::MAX as f32;
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(self.0 as i16) as f32 * adc_volts_per_lsb
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}
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}
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// The following data is written by the timer ADC sample trigger into the SPI CR1 to start the
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// transfer. Data in AXI SRAM is not initialized on boot, so the contents are random. This value is
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// initialized during setup.
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#[link_section = ".axisram.buffers"]
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static mut SPI_START: [u32; 1] = [0x00; 1];
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// The following data is written by the timer flag clear trigger into the SPI IFCR register to clear
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// the EOT flag. Data in AXI SRAM is not initialized on boot, so the contents are random. This
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// value is initialized during setup.
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#[link_section = ".axisram.buffers"]
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static mut SPI_EOT_CLEAR: [u32; 1] = [0x00];
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// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined. The dimensions are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut ADC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 2]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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macro_rules! adc_input {
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($name:ident, $index:literal, $trigger_stream:ident, $data_stream:ident, $clear_stream:ident,
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$spi:ident, $trigger_channel:ident, $dma_req:ident, $clear_channel:ident, $dma_clear_req:ident) => {
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paste::paste! {
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/// $spi-CR is used as a type for indicating a DMA transfer into the SPI control
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/// register whenever the tim2 update dma request occurs.
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struct [< $spi CR >] {
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_channel: timers::tim2::$trigger_channel,
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}
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impl [< $spi CR >] {
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pub fn new(_channel: timers::tim2::$trigger_channel) -> Self {
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Self { _channel }
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}
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}
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// Note(unsafe): This structure is only safe to instantiate once. The DMA request is
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// hard-coded and may only be used if ownership of the timer2 $trigger_channel compare
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// channel is assured, which is ensured by maintaining ownership of the channel.
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unsafe impl TargetAddress<MemoryToPeripheral> for [< $spi CR >] {
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type MemSize = u32;
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/// SPI DMA requests are generated whenever TIM2 CHx ($dma_req) comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::$dma_req as u8);
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/// Whenever the DMA request occurs, it should write into SPI's CR1 to start the
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/// transfer.
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fn address(&self) -> usize {
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// Note(unsafe): It is assumed that SPI is owned by another DMA transfer. This
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// is only safe because we are writing to a configuration register.
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let regs = unsafe { &*hal::stm32::$spi::ptr() };
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®s.cr1 as *const _ as usize
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}
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}
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/// $spi-IFCR is used as a type for indicating a DMA transfer into the SPI flag clear
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/// register whenever the tim3 compare dma request occurs. The flag must be cleared
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/// before the transfer starts.
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struct [< $spi IFCR >] {
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_channel: timers::tim3::$clear_channel,
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}
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impl [< $spi IFCR >] {
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pub fn new(_channel: timers::tim3::$clear_channel) -> Self {
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Self { _channel }
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}
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}
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// Note(unsafe): This structure is only safe to instantiate once. The DMA request is
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// hard-coded and may only be used if ownership of the timer3 $clear_channel compare
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// channel is assured, which is ensured by maintaining ownership of the channel.
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unsafe impl TargetAddress<MemoryToPeripheral> for [< $spi IFCR >] {
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type MemSize = u32;
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/// SPI DMA requests are generated whenever TIM3 CHx ($dma_clear_req) comparison
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/// occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::$dma_clear_req as u8);
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/// Whenever the DMA request occurs, it should write into SPI's IFCR to clear the
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/// EOT flag to allow the next transmission.
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fn address(&self) -> usize {
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// Note(unsafe): It is assumed that SPI is owned by another DMA transfer and
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// this DMA is only used for writing to the configuration registers.
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let regs = unsafe { &*hal::stm32::$spi::ptr() };
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®s.ifcr as *const _ as usize
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}
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}
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/// Represents data associated with ADC.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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PeripheralToMemory,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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hal::dma::DBTransfer,
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>,
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trigger_transfer: Transfer<
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hal::dma::dma::$trigger_stream<hal::stm32::DMA1>,
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[< $spi CR >],
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MemoryToPeripheral,
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&'static mut [u32; 1],
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hal::dma::DBTransfer,
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>,
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clear_transfer: Transfer<
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hal::dma::dma::$clear_stream<hal::stm32::DMA1>,
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[< $spi IFCR >],
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MemoryToPeripheral,
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&'static mut [u32; 1],
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hal::dma::DBTransfer,
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>,
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}
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impl $name {
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/// Construct the ADC input channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by
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/// writing a word into the SPI TX FIFO.
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/// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer.
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/// * `clear_stream` - The DMA stream used to clear the EOT flag in the SPI peripheral.
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/// * `trigger_channel` - The ADC sampling timer output compare channel for read triggers.
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/// * `clear_channel` - The shadow sampling timer output compare channel used for
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/// clearing the SPI EOT flag.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Enabled, u16>,
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trigger_stream: hal::dma::dma::$trigger_stream<
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hal::stm32::DMA1,
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>,
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data_stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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clear_stream: hal::dma::dma::$clear_stream<hal::stm32::DMA1>,
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trigger_channel: timers::tim2::$trigger_channel,
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clear_channel: timers::tim3::$clear_channel,
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) -> Self {
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// The flag clear DMA transfer always clears the EOT flag in the SPI
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// peripheral. It has the highest priority to ensure it is completed before the
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// transfer trigger.
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let clear_config = DmaConfig::default()
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.priority(Priority::VeryHigh)
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.circular_buffer(true);
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unsafe {
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SPI_EOT_CLEAR[0] = 1 << 3;
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}
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// Generate DMA events when the timer hits zero (roll-over). This must be before
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// the trigger channel DMA occurs, as if the trigger occurs first, the
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// transmission will not occur.
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clear_channel.listen_dma();
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clear_channel.to_output_compare(0);
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let clear_transfer: Transfer<
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_,
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_,
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MemoryToPeripheral,
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_,
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_,
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> = Transfer::init(
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clear_stream,
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[< $spi IFCR >]::new(clear_channel),
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// Note(unsafe): Because this is a Memory->Peripheral transfer, this data is
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// never actually modified. It technically only needs to be immutably
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// borrowed, but the current HAL API only supports mutable borrows.
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unsafe { &mut SPI_EOT_CLEAR },
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None,
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clear_config,
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);
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// Generate DMA events when an output compare of the timer hits the specified
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// value.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(2 + $index);
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// The trigger stream constantly writes to the SPI CR1 using a static word
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// (which is a static value to enable the SPI transfer). Thus, neither the
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// memory or peripheral address ever change. This is run in circular mode to be
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// completed at every DMA request.
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let trigger_config = DmaConfig::default()
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.priority(Priority::High)
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.circular_buffer(true);
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// Note(unsafe): This word is initialized once per ADC initialization to verify
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// it is initialized properly.
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unsafe {
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// Write a binary code into the SPI control register to initiate a transfer.
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SPI_START[0] = 0x201;
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};
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// Construct the trigger stream to write from memory to the peripheral.
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let trigger_transfer: Transfer<
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_,
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_,
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MemoryToPeripheral,
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_,
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_,
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> = Transfer::init(
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trigger_stream,
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[< $spi CR >]::new(trigger_channel),
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// Note(unsafe): Because this is a Memory->Peripheral transfer, this data is never
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// actually modified. It technically only needs to be immutably borrowed, but the
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// current HAL API only supports mutable borrows.
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unsafe { &mut SPI_START },
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None,
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trigger_config,
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);
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// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
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// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
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// after the requested number of samples have been collected. Note that only ADC1's (sic!)
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// data stream is used to trigger a transfer completion interrupt.
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let data_config = DmaConfig::default()
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.memory_increment(true)
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.transfer_complete_interrupt($index == 1)
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.priority(Priority::VeryHigh);
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// A SPI peripheral error interrupt is used to determine if the RX FIFO
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// overflows. This indicates that samples were dropped due to excessive
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// processing time in the main application (e.g. a second DMA transfer completes
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// before the first was done with processing). This is used as a flow control
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// indicator to guarantee that no ADC samples are lost.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// The data transfer is always a transfer of data from the peripheral to a RAM
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// buffer.
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let data_transfer: Transfer<_, _, PeripheralToMemory, _, _> =
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Transfer::init(
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data_stream,
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spi,
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// Note(unsafe): The ADC_BUF[$index][0] is "owned" by this peripheral.
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// It shall not be used anywhere else in the module.
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unsafe { &mut ADC_BUF[$index][0] },
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None,
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data_config,
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);
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Self {
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// Note(unsafe): The ADC_BUF[$index][1] is "owned" by this peripheral. It
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// shall not be used anywhere else in the module.
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next_buffer: unsafe { Some(&mut ADC_BUF[$index][1]) },
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transfer: data_transfer,
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trigger_transfer,
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clear_transfer,
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}
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}
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/// Enable the ADC DMA transfer sequence.
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pub fn start(&mut self) {
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self.transfer.start(|spi| {
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spi.enable_dma_rx();
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spi.inner().cr2.modify(|_, w| w.tsize().bits(1));
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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});
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self.clear_transfer.start(|_| {});
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self.trigger_transfer.start(|_| {});
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}
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/// Obtain a buffer filled with ADC samples.
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///
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/// # Returns
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/// A reference to the underlying buffer that has been filled with ADC samples.
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pub fn acquire_buffer(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] {
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// Wait for the transfer to fully complete before continuing. Note: If a device
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// hangs up, check that this conditional is passing correctly, as there is no
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// time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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let next_buffer = self.next_buffer.take().unwrap();
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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self.next_buffer.replace(prev_buffer);
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self.next_buffer.as_ref().unwrap()
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}
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}
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}
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};
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}
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adc_input!(
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Adc0Input, 0, Stream0, Stream1, Stream2, SPI2, Channel1, TIM2_CH1,
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Channel1, TIM3_CH1
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);
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adc_input!(
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Adc1Input, 1, Stream3, Stream4, Stream5, SPI3, Channel2, TIM2_CH2,
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Channel2, TIM3_CH2
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);
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