47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
MEMORY
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{
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ITCM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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AXISRAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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SRAM1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
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SRAM2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
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SRAM3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
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BACKUPSRAM (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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RAM_B (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH1 (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
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}
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SECTIONS {
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.axisram (NOLOAD) : ALIGN(8) {
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*(.axisram .axisram.*);
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. = ALIGN(8);
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} > AXISRAM
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.sram1 (NOLOAD) : ALIGN(4) {
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*(.sram1 .sram1.*);
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. = ALIGN(4);
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} > SRAM1
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.sram2 (NOLOAD) : ALIGN(4) {
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*(.sram2 .sram2.*);
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. = ALIGN(4);
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} > SRAM2
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.sram3 (NOLOAD) : ALIGN(4) {
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*(.sram3 .sram3.*);
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. = ALIGN(4);
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} > SRAM3
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.itcm : ALIGN(8) {
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. = ALIGN(8);
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__sitcm = .;
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*(.itcm .itcm.*);
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. = ALIGN(8);
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__eitcm = .;
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} > ITCM AT>FLASH
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__siitcm = LOADADDR(.itcm);
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} INSERT AFTER .uninit;
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ASSERT(__sitcm % 8 == 0 && __eitcm % 8 == 0, "
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BUG(cortex-m-rt): .itcm is not 8-byte aligned");
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ASSERT(__siitcm % 4 == 0, "
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BUG(cortex-m-rt): the LMA of .itcm is not 4-byte aligned");
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