637 lines
20 KiB
Rust
637 lines
20 KiB
Rust
#![no_std]
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use bit_field::BitField;
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use embedded_hal::{blocking::delay::DelayUs, digital::v2::OutputPin};
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/// A device driver for the AD9959 direct digital synthesis (DDS) chip.
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///
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/// This chip provides four independently controllable digital-to-analog output sinusoids with
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/// configurable phase, amplitude, and frequency. All channels are inherently synchronized as they
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/// are derived off a common system clock.
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///
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/// The chip contains a configurable PLL and supports system clock frequencies up to 500 MHz.
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///
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/// The chip supports a number of serial interfaces to improve data throughput, including normal,
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/// dual, and quad SPI configurations.
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pub struct Ad9959<INTERFACE> {
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interface: INTERFACE,
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reference_clock_frequency: f32,
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system_clock_multiplier: u8,
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communication_mode: Mode,
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}
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/// A trait that allows a HAL to provide a means of communicating with the AD9959.
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pub trait Interface {
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type Error;
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fn configure_mode(&mut self, mode: Mode) -> Result<(), Self::Error>;
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fn write(&mut self, addr: u8, data: &[u8]) -> Result<(), Self::Error>;
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fn read(&mut self, addr: u8, dest: &mut [u8]) -> Result<(), Self::Error>;
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}
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/// Indicates various communication modes of the DDS. The value of this enumeration is equivalent to
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/// the configuration bits of the DDS CSR register.
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#[derive(Copy, Clone, PartialEq)]
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#[repr(u8)]
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pub enum Mode {
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SingleBitTwoWire = 0b00,
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SingleBitThreeWire = 0b01,
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TwoBitSerial = 0b10,
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FourBitSerial = 0b11,
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}
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/// The configuration registers within the AD9959 DDS device. The values of each register are
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/// equivalent to the address.
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#[allow(clippy::upper_case_acronyms)]
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pub enum Register {
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CSR = 0x00,
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FR1 = 0x01,
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FR2 = 0x02,
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CFR = 0x03,
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CFTW0 = 0x04,
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CPOW0 = 0x05,
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ACR = 0x06,
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LSRR = 0x07,
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RDW = 0x08,
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FDW = 0x09,
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CW1 = 0x0a,
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CW2 = 0x0b,
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CW3 = 0x0c,
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CW4 = 0x0d,
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CW5 = 0x0e,
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CW6 = 0x0f,
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CW7 = 0x10,
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CW8 = 0x11,
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CW9 = 0x12,
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CW10 = 0x13,
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CW11 = 0x14,
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CW12 = 0x15,
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CW13 = 0x16,
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CW14 = 0x17,
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CW15 = 0x18,
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}
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/// Specifies an output channel of the AD9959 DDS chip.
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#[derive(Copy, Clone, PartialEq)]
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pub enum Channel {
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One = 0,
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Two = 1,
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Three = 2,
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Four = 3,
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}
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/// Possible errors generated by the AD9959 driver.
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#[derive(Debug)]
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pub enum Error {
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Interface,
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Check,
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Bounds,
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Pin,
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Frequency,
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}
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impl<I: Interface> Ad9959<I> {
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/// Construct and initialize the DDS.
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///
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/// Args:
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/// * `interface` - An interface to the DDS.
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/// * `reset_pin` - A pin connected to the DDS reset input.
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/// * `io_update` - A pin connected to the DDS io_update input.
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/// * `delay` - A delay implementation for blocking operation for specific amounts of time.
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/// * `desired_mode` - The desired communication mode of the interface to the DDS.
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/// * `clock_frequency` - The clock frequency of the reference clock input.
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/// * `multiplier` - The desired clock multiplier for the system clock. This multiplies
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/// `clock_frequency` to generate the system clock.
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pub fn new(
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interface: I,
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mut reset_pin: impl OutputPin,
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io_update: &mut impl OutputPin,
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delay: &mut impl DelayUs<u8>,
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desired_mode: Mode,
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clock_frequency: f32,
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multiplier: u8,
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) -> Result<Self, Error> {
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let mut ad9959 = Ad9959 {
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interface,
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reference_clock_frequency: clock_frequency,
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system_clock_multiplier: 1,
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communication_mode: desired_mode,
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};
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io_update.set_low().or(Err(Error::Pin))?;
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// Reset the AD9959
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reset_pin.set_high().or(Err(Error::Pin))?;
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// Delay for at least 1 SYNC_CLK period for the reset to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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reset_pin.set_low().or(Err(Error::Pin))?;
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ad9959
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.interface
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.configure_mode(Mode::SingleBitTwoWire)
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.or(Err(Error::Interface))?;
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// Program the interface configuration in the AD9959. Default to all channels enabled.
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let mut csr: [u8; 1] = [0xF0];
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csr[0].set_bits(1..3, desired_mode as u8);
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ad9959.write(Register::CSR, &csr)?;
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// Latch the new interface configuration.
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io_update.set_high().or(Err(Error::Pin))?;
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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io_update.set_low().or(Err(Error::Pin))?;
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ad9959
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.interface
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.configure_mode(desired_mode)
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.or(Err(Error::Interface))?;
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// Empirical evidence indicates a delay is necessary here for the IO update to become
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// active. This is likely due to needing to wait at least 1 clock cycle of the DDS for the
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// interface update to occur.
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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// Read back the CSR to ensure it specifies the mode correctly.
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let mut updated_csr: [u8; 1] = [0];
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ad9959.read(Register::CSR, &mut updated_csr)?;
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if updated_csr[0] != csr[0] {
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return Err(Error::Check);
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}
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// Set the clock frequency to configure the device as necessary.
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ad9959.configure_system_clock(clock_frequency, multiplier)?;
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// Latch the new clock configuration.
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io_update.set_high().or(Err(Error::Pin))?;
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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io_update.set_low().or(Err(Error::Pin))?;
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Ok(ad9959)
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}
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fn read(&mut self, reg: Register, data: &mut [u8]) -> Result<(), Error> {
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self.interface
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.read(reg as u8, data)
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.or(Err(Error::Interface))
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}
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fn write(&mut self, reg: Register, data: &[u8]) -> Result<(), Error> {
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self.interface
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.write(reg as u8, data)
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.or(Err(Error::Interface))
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}
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/// Configure the internal system clock of the chip.
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///
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/// Arguments:
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/// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core.
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/// * `multiplier` - The frequency multiplier of the system clock. Must be 1 or 4-20.
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///
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/// Returns:
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/// The actual frequency configured for the internal system clock.
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fn configure_system_clock(
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&mut self,
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reference_clock_frequency: f32,
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multiplier: u8,
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) -> Result<f32, Error> {
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self.reference_clock_frequency = reference_clock_frequency;
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if multiplier != 1 && !(4..=20).contains(&multiplier) {
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return Err(Error::Bounds);
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}
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let frequency =
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multiplier as f32 * self.reference_clock_frequency as f32;
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if frequency > 500_000_000.0f32 {
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return Err(Error::Frequency);
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}
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// TODO: Update / disable any enabled channels?
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let mut fr1: [u8; 3] = [0, 0, 0];
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self.read(Register::FR1, &mut fr1)?;
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fr1[0].set_bits(2..=6, multiplier);
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let vco_range = frequency > 255e6;
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fr1[0].set_bit(7, vco_range);
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self.write(Register::FR1, &fr1)?;
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self.system_clock_multiplier = multiplier;
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Ok(self.system_clock_frequency())
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}
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/// Get the current reference clock frequency in Hz.
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pub fn get_reference_clock_frequency(&self) -> f32 {
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self.reference_clock_frequency
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}
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/// Get the current reference clock multiplier.
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pub fn get_reference_clock_multiplier(&mut self) -> Result<u8, Error> {
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let mut fr1: [u8; 3] = [0, 0, 0];
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self.read(Register::FR1, &mut fr1)?;
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Ok(fr1[0].get_bits(2..=6) as u8)
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}
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/// Perform a self-test of the communication interface.
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///
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/// Note:
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/// This modifies the existing channel enables. They are restored upon exit.
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///
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/// Returns:
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/// True if the self test succeeded. False otherwise.
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pub fn self_test(&mut self) -> Result<bool, Error> {
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let mut csr: [u8; 1] = [0];
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self.read(Register::CSR, &mut csr)?;
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let old_csr = csr[0];
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// Enable all channels.
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csr[0].set_bits(4..8, 0xF);
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self.write(Register::CSR, &csr)?;
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// Read back the enable.
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csr[0] = 0;
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self.read(Register::CSR, &mut csr)?;
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if csr[0].get_bits(4..8) != 0xF {
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return Ok(false);
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}
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// Clear all channel enables.
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csr[0].set_bits(4..8, 0x0);
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self.write(Register::CSR, &csr)?;
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// Read back the enable.
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csr[0] = 0xFF;
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self.read(Register::CSR, &mut csr)?;
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if csr[0].get_bits(4..8) != 0 {
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return Ok(false);
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}
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// Restore the CSR.
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csr[0] = old_csr;
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self.write(Register::CSR, &csr)?;
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Ok(true)
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}
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/// Get the current system clock frequency in Hz.
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fn system_clock_frequency(&self) -> f32 {
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self.system_clock_multiplier as f32
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* self.reference_clock_frequency as f32
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}
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/// Update an output channel configuration register.
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///
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/// Args:
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/// * `channel` - The channel to configure.
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/// * `register` - The register to update.
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/// * `data` - The contents to write to the provided register.
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fn modify_channel(
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&mut self,
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channel: Channel,
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register: Register,
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data: &[u8],
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) -> Result<(), Error> {
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// Disable all other outputs so that we can update the configuration register of only the
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// specified channel.
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let csr: u8 = *0x00_u8
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.set_bits(1..=2, self.communication_mode as u8)
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.set_bit(4 + channel as usize, true);
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self.interface
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.write(Register::CSR as u8, &[csr])
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.map_err(|_| Error::Interface)?;
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self.write(register, data)?;
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Ok(())
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}
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/// Read a configuration register of a specific channel.
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///
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/// Args:
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/// * `channel` - The channel to read.
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/// * `register` - The register to read.
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/// * `data` - A location to store the read register contents.
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fn read_channel(
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&mut self,
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channel: Channel,
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register: Register,
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mut data: &mut [u8],
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) -> Result<(), Error> {
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// Disable all other channels in the CSR so that we can read the configuration register of
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// only the desired channel.
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let mut csr: [u8; 1] = [0];
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self.read(Register::CSR, &mut csr)?;
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let mut new_csr = csr;
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new_csr[0].set_bits(4..8, 0);
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new_csr[0].set_bit(4 + channel as usize, true);
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self.write(Register::CSR, &new_csr)?;
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self.read(register, &mut data)?;
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// Restore the previous CSR. Note that the re-enable of the channel happens immediately, so
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// the CSR update does not need to be latched.
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self.write(Register::CSR, &csr)?;
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Ok(())
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}
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/// Configure the phase of a specified channel.
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///
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/// Arguments:
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/// * `channel` - The channel to configure the frequency of.
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/// * `phase_turns` - The desired phase offset in turns.
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///
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/// Returns:
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/// The actual programmed phase offset of the channel in turns.
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pub fn set_phase(
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&mut self,
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channel: Channel,
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phase_turns: f32,
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) -> Result<f32, Error> {
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let phase_offset: u16 =
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(phase_turns * (1 << 14) as f32) as u16 & 0x3FFFu16;
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self.modify_channel(
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channel,
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Register::CPOW0,
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&phase_offset.to_be_bytes(),
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)?;
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Ok((phase_offset as f32) / ((1 << 14) as f32))
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}
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/// Get the current phase of a specified channel.
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///
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/// Args:
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/// * `channel` - The channel to get the phase of.
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///
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/// Returns:
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/// The phase of the channel in turns.
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pub fn get_phase(&mut self, channel: Channel) -> Result<f32, Error> {
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let mut phase_offset: [u8; 2] = [0; 2];
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self.read_channel(channel, Register::CPOW0, &mut phase_offset)?;
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let phase_offset = u16::from_be_bytes(phase_offset) & 0x3FFFu16;
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Ok((phase_offset as f32) / ((1 << 14) as f32))
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}
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/// Configure the amplitude of a specified channel.
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///
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/// Arguments:
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/// * `channel` - The channel to configure the frequency of.
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/// * `amplitude` - A normalized amplitude setting [0, 1].
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///
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/// Returns:
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/// The actual normalized amplitude of the channel relative to full-scale range.
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pub fn set_amplitude(
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&mut self,
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channel: Channel,
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amplitude: f32,
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) -> Result<f32, Error> {
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if !(0.0..=1.0).contains(&litude) {
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return Err(Error::Bounds);
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}
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let amplitude_control: u16 = (amplitude * (1 << 10) as f32) as u16;
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let mut acr: [u8; 3] = [0; 3];
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// Enable the amplitude multiplier for the channel if required. The amplitude control has
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// full-scale at 0x3FF (amplitude of 1), so the multiplier should be disabled whenever
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// full-scale is used.
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if amplitude_control < (1 << 10) {
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let masked_control = amplitude_control & 0x3FF;
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acr[1] = masked_control.to_be_bytes()[0];
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acr[2] = masked_control.to_be_bytes()[1];
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// Enable the amplitude multiplier
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acr[1].set_bit(4, true);
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}
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self.modify_channel(channel, Register::ACR, &acr)?;
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Ok(amplitude_control as f32 / (1 << 10) as f32)
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}
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/// Get the configured amplitude of a channel.
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///
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/// Args:
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/// * `channel` - The channel to get the amplitude of.
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///
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/// Returns:
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/// The normalized amplitude of the channel.
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pub fn get_amplitude(&mut self, channel: Channel) -> Result<f32, Error> {
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let mut acr: [u8; 3] = [0; 3];
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self.read_channel(channel, Register::ACR, &mut acr)?;
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if acr[1].get_bit(4) {
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let amplitude_control: u16 =
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(((acr[1] as u16) << 8) | (acr[2] as u16)) & 0x3FF;
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Ok(amplitude_control as f32 / (1 << 10) as f32)
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} else {
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Ok(1.0)
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}
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}
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/// Configure the frequency of a specified channel.
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///
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/// Arguments:
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/// * `channel` - The channel to configure the frequency of.
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/// * `frequency` - The desired output frequency in Hz.
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///
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/// Returns:
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/// The actual programmed frequency of the channel.
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pub fn set_frequency(
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&mut self,
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channel: Channel,
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frequency: f32,
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) -> Result<f32, Error> {
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if frequency < 0.0 || frequency > self.system_clock_frequency() {
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return Err(Error::Bounds);
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}
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// The function for channel frequency is `f_out = FTW * f_s / 2^32`, where FTW is the
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// frequency tuning word and f_s is the system clock rate.
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let tuning_word: u32 =
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((frequency as f32 / self.system_clock_frequency())
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* 1u64.wrapping_shl(32) as f32) as u32;
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self.modify_channel(
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channel,
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Register::CFTW0,
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&tuning_word.to_be_bytes(),
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)?;
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Ok((tuning_word as f32 / 1u64.wrapping_shl(32) as f32)
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* self.system_clock_frequency())
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}
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/// Get the frequency of a channel.
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///
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/// Arguments:
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/// * `channel` - The channel to get the frequency of.
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///
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/// Returns:
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/// The frequency of the channel in Hz.
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pub fn get_frequency(&mut self, channel: Channel) -> Result<f32, Error> {
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// Read the frequency tuning word for the channel.
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let mut tuning_word: [u8; 4] = [0; 4];
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self.read_channel(channel, Register::CFTW0, &mut tuning_word)?;
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let tuning_word = u32::from_be_bytes(tuning_word);
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// Convert the tuning word into a frequency.
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Ok((tuning_word as f32 * self.system_clock_frequency())
|
|
/ (1u64 << 32) as f32)
|
|
}
|
|
|
|
/// Finalize DDS configuration
|
|
///
|
|
/// # Note
|
|
/// This is intended for when the DDS profiles will be written as a stream of data to the DDS.
|
|
///
|
|
/// # Returns
|
|
/// (I, config) where `I` is the interface to the DDS and `config` is the frozen `DdsConfig`.
|
|
pub fn freeze(self) -> (I, DdsConfig) {
|
|
let config = DdsConfig {
|
|
mode: self.communication_mode,
|
|
};
|
|
(self.interface, config)
|
|
}
|
|
}
|
|
|
|
/// The frozen DDS configuration.
|
|
pub struct DdsConfig {
|
|
mode: Mode,
|
|
}
|
|
|
|
impl DdsConfig {
|
|
/// Create a serializer that can be used for generating a serialized DDS profile for writing to
|
|
/// a QSPI stream.
|
|
pub fn serializer(&self) -> ProfileSerializer {
|
|
ProfileSerializer::new(self.mode)
|
|
}
|
|
}
|
|
|
|
/// Represents a means of serializing a DDS profile for writing to a stream.
|
|
pub struct ProfileSerializer {
|
|
data: [u8; 16],
|
|
index: usize,
|
|
mode: Mode,
|
|
}
|
|
|
|
impl ProfileSerializer {
|
|
/// Construct a new serializer.
|
|
///
|
|
/// # Args
|
|
/// * `mode` - The communication mode of the DDS.
|
|
fn new(mode: Mode) -> Self {
|
|
Self {
|
|
mode,
|
|
data: [0; 16],
|
|
index: 0,
|
|
}
|
|
}
|
|
|
|
/// Update a number of channels with the requested profile.
|
|
///
|
|
/// # Args
|
|
/// * `channels` - A list of channels to apply the configuration to.
|
|
/// * `ftw` - If provided, indicates a frequency tuning word for the channels.
|
|
/// * `pow` - If provided, indicates a phase offset word for the channels.
|
|
/// * `acr` - If provided, indicates the amplitude control register for the channels. The ACR
|
|
/// should be stored in the 3 LSB of the word. Note that if amplitude scaling is to be used,
|
|
/// the "Amplitude multiplier enable" bit must be set.
|
|
#[inline]
|
|
pub fn update_channels(
|
|
&mut self,
|
|
channels: &[Channel],
|
|
ftw: Option<u32>,
|
|
pow: Option<u16>,
|
|
acr: Option<u32>,
|
|
) {
|
|
let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8);
|
|
for channel in channels.iter() {
|
|
csr.set_bit(4 + *channel as usize, true);
|
|
}
|
|
|
|
self.add_write(Register::CSR, &[csr]);
|
|
|
|
if let Some(ftw) = ftw {
|
|
self.add_write(Register::CFTW0, &ftw.to_be_bytes());
|
|
}
|
|
|
|
if let Some(pow) = pow {
|
|
self.add_write(Register::CPOW0, &pow.to_be_bytes());
|
|
}
|
|
|
|
if let Some(acr) = acr {
|
|
self.add_write(Register::ACR, &acr.to_be_bytes()[1..]);
|
|
}
|
|
}
|
|
|
|
/// Add a register write to the serialization data.
|
|
fn add_write(&mut self, register: Register, value: &[u8]) {
|
|
let data = &mut self.data[self.index..];
|
|
data[0] = register as u8;
|
|
data[1..][..value.len()].copy_from_slice(value);
|
|
self.index += value.len() + 1;
|
|
}
|
|
|
|
#[inline]
|
|
fn pad(&mut self) {
|
|
// Pad the buffer to 32-bit (4 byte) alignment by adding dummy writes to CSR and LSRR.
|
|
// In the case of 1 byte padding, this instead pads with 5 bytes as there is no
|
|
// valid single-byte write that could be used.
|
|
if self.index & 1 != 0 {
|
|
// Pad with 3 bytes
|
|
self.add_write(Register::LSRR, &[0, 0]);
|
|
}
|
|
if self.index & 2 != 0 {
|
|
// Pad with 2 bytes
|
|
self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
|
|
}
|
|
debug_assert_eq!(self.index & 3, 0);
|
|
}
|
|
|
|
/// Get the serialized profile as a slice of 32-bit words.
|
|
///
|
|
/// # Note
|
|
/// The serialized profile will be padded to the next 32-bit word boundary by adding dummy
|
|
/// writes to the CSR or LSRR registers.
|
|
///
|
|
/// # Returns
|
|
/// A slice of `u32` words representing the serialized profile.
|
|
#[inline]
|
|
pub fn finalize<'a>(&'a mut self) -> &'a [u32] {
|
|
self.pad();
|
|
unsafe {
|
|
core::slice::from_raw_parts::<'a, u32>(
|
|
&self.data as *const _ as *const u32,
|
|
self.index / 4,
|
|
)
|
|
}
|
|
}
|
|
}
|