635 lines
23 KiB
Rust
635 lines
23 KiB
Rust
//#![deny(warnings)]
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#![allow(clippy::missing_safety_doc)]
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#![no_std]
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#![no_main]
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#![cfg_attr(feature = "nightly", feature(asm))]
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// Enable returning `!`
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#![cfg_attr(feature = "nightly", feature(never_type))]
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#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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#[inline(never)]
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#[panic_handler]
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#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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let gpiod = unsafe { &*pac::GPIOD::ptr() };
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gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
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unsafe {
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core::intrinsics::abort();
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}
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}
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#[cfg(feature = "semihosting")]
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extern crate panic_semihosting;
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#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
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extern crate panic_halt;
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#[macro_use]
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extern crate log;
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use nb;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use asm_delay;
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use rtfm::cyccnt::{Instant, U32Ext};
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use cortex_m_rt::exception;
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use cortex_m;
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::{
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prelude::*,
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stm32 as pac,
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};
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use embedded_hal::{
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digital::v2::OutputPin,
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};
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use stm32h7_ethernet as ethernet;
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use smoltcp as net;
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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mod eth;
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mod pounder;
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mod server;
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mod afe;
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mod iir;
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use iir::*;
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mod eeprom;
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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#[cfg(feature = "semihosting")]
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fn init_log() {
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use cortex_m_log::log::{init as init_log, Logger};
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use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
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};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
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// Pull in build information (from `built` crate)
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mod build_info {
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#![allow(dead_code)]
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// include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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pub struct NetStorage {
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ip_addrs: [net::wire::IpCidr; 1],
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neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
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}
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [net::wire::IpCidr::Ipv6(net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX)],
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neighbor_cache: [None; 8],
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};
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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const SPI_START_CODE: u32 = 0x201;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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type AFE1 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>>;
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type AFE2 = afe::ProgrammableGainAmplifier<
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hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>>;
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#[rtfm::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtfm::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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adc1: hal::spi::Spi<hal::stm32::SPI2>,
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dac1: hal::spi::Spi<hal::stm32::SPI4>,
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_afe1: AFE1,
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adc2: hal::spi::Spi<hal::stm32::SPI3>,
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dac2: hal::spi::Spi<hal::stm32::SPI5>,
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_afe2: AFE2,
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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timer: hal::timer::Timer<hal::stm32::TIM2>,
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net_interface: net::iface::EthernetInterface<'static, 'static, 'static,
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ethernet::EthernetDMA<'static>>,
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_eth_mac: ethernet::EthernetMAC,
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mac_addr: net::wire::EthernetAddress,
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//pounder: pounder::PounderDevices<asm_delay::AsmDelay>,
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#[init([[0.; 5]; 2])]
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iir_state: [IIRState; 2],
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#[init([IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
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iir_ch: [IIR; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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let dp = c.device;
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let mut clocks = rcc
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//TODO: Re-enable HSE for Stabilizer platform.
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// .use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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// Enable SRAM3 for the ethernet descriptor ring.
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clocks.rb.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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clocks.rb.rsr.write(|w| w.rmvf().set_bit());
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clocks.rb.d2ccip1r.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks);
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let gpioa = dp.GPIOA.split(&mut clocks.ahb4);
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let gpiob = dp.GPIOB.split(&mut clocks.ahb4);
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let gpioc = dp.GPIOC.split(&mut clocks.ahb4);
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let gpiod = dp.GPIOD.split(&mut clocks.ahb4);
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let gpioe = dp.GPIOE.split(&mut clocks.ahb4);
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let gpiof = dp.GPIOF.split(&mut clocks.ahb4);
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let gpiog = dp.GPIOG.split(&mut clocks.ahb4);
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let afe1 = {
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let a0_pin = gpiof.pf2.into_push_pull_output();
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let a1_pin = gpiof.pf5.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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let afe2 = {
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let a0_pin = gpiod.pd14.into_push_pull_output();
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let a1_pin = gpiod.pd15.into_push_pull_output();
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afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
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};
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc1_spi = {
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let spi_miso = gpiob.pb14.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiob.pb10.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiob.pb9.into_alternate_af5();
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.communication_mode(hal::spi::CommunicationMode::Receiver)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.cs_delay(220e-9);
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let mut spi = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks);
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spi.listen(hal::spi::Event::Eot);
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spi
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};
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let adc2_spi = {
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let spi_miso = gpiob.pb4.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioc.pc10.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioa.pa15.into_alternate_af6();
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.communication_mode(hal::spi::CommunicationMode::Receiver)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.cs_delay(220e-9);
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let mut spi = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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50.mhz(),
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&clocks);
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spi.listen(hal::spi::Event::Eot);
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spi
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};
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let dac1_spi = {
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let spi_miso = gpioe.pe5.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioe.pe2.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioe.pe4.into_alternate_af5();
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.swap_mosi_miso();
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let spi = dp.SPI4.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks);
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spi
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};
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let dac2_spi = {
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let spi_miso = gpiof.pf8.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiof.pf7.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiof.pf6.into_alternate_af5();
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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.communication_mode(hal::spi::CommunicationMode::Transmitter)
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.manage_cs()
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.transfer_size(1)
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.frame_size(16)
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.swap_mosi_miso();
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let spi = dp.SPI5.spi((spi_sck, spi_miso, hal::spi::NoMosi), config, 50.mhz(), &clocks);
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spi
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};
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// let pounder_devices = {
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// let ad9959 = {
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// let qspi_interface = {
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// // Instantiate the QUADSPI pins and peripheral interface.
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// // TODO: Place these into a pins structure that is provided to the QSPI
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// // constructor.
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// let _qspi_clk = gpiob.pb2.into_alternate_af9();
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// let _qspi_ncs = gpioc.pc11.into_alternate_af9();
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// let _qspi_io0 = gpioe.pe7.into_alternate_af10();
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// let _qspi_io1 = gpioe.pe8.into_alternate_af10();
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// let _qspi_io2 = gpioe.pe9.into_alternate_af10();
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// let _qspi_io3 = gpioe.pe10.into_alternate_af10();
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// let qspi = hal::qspi::Qspi::new(dp.QUADSPI, &mut clocks, 10.mhz()).unwrap();
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// pounder::QspiInterface::new(qspi).unwrap()
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// };
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// let mut reset_pin = gpioa.pa0.into_push_pull_output();
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// let io_update = gpiog.pg7.into_push_pull_output();
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// let asm_delay = {
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// let frequency_hz = clocks.clocks.c_ck().0;
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// asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz (frequency_hz))
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// };
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// ad9959::Ad9959::new(qspi_interface,
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// &mut reset_pin,
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// io_update,
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// asm_delay,
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// ad9959::Mode::FourBitSerial,
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// 100_000_000,
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// 5).unwrap()
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// };
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// let io_expander = {
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// let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
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// let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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// let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), &clocks);
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// mcp23017::MCP23017::default(i2c1).unwrap()
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// };
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// let spi = {
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// let spi_mosi = gpiod.pd7.into_alternate_af5();
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// let spi_miso = gpioa.pa6.into_alternate_af5();
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// let spi_sck = gpiog.pg11.into_alternate_af5();
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// let config = hal::spi::Config::new(hal::spi::Mode{
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// polarity: hal::spi::Polarity::IdleHigh,
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// phase: hal::spi::Phase::CaptureOnSecondTransition,
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// })
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// .frame_size(8);
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// dp.SPI1.spi((spi_sck, spi_miso, spi_mosi), config, 25.mhz(), &clocks)
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// };
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// let adc1 = {
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// let mut adc = dp.ADC1.adc(&mut delay, &mut clocks);
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// adc.calibrate();
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// adc.enable()
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// };
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// let adc2 = {
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// let mut adc = dp.ADC2.adc(&mut delay, &mut clocks);
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// adc.calibrate();
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// adc.enable()
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// };
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// let adc1_in_p = gpiof.pf11.into_analog();
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// let adc2_in_p = gpiof.pf14.into_analog();
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// pounder::PounderDevices::new(io_expander,
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// ad9959,
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// spi,
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// adc1,
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// adc2,
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// adc1_in_p,
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// adc2_in_p).unwrap()
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// };
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let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
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let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
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let mut fp_led_2 = gpiod.pd12.into_push_pull_output();
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let mut fp_led_3 = gpiog.pg4.into_push_pull_output();
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fp_led_0.set_low().unwrap();
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fp_led_1.set_low().unwrap();
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fp_led_2.set_low().unwrap();
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fp_led_3.set_low().unwrap();
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let mut eeprom_i2c = {
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let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
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let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
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dp.I2C2.i2c((scl, sda), 100.khz(), &clocks)
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};
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// Configure ethernet pins.
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{
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// Reset the PHY before configuring pins.
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let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
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eth_phy_nrst.set_high().unwrap();
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eth_phy_nrst.set_low().unwrap();
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eth_phy_nrst.set_high().unwrap();
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let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_tx_en = gpiob.pb11.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_txd0 = gpiob.pb12.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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let _rmii_txd1 = gpiog.pg14.into_alternate_af11().set_speed(hal::gpio::Speed::VeryHigh);
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}
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let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
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Err(_) => {
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info!("Could not read EEPROM, using default MAC address");
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net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
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}
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Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
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};
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let (network_interface, eth_mac) = {
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// Configure the ethernet controller
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let (eth_dma, eth_mac) = unsafe {
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ethernet::ethernet_init(
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dp.ETHERNET_MAC,
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dp.ETHERNET_MTL,
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dp.ETHERNET_DMA,
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&mut DES_RING,
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mac_addr.clone())
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};
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let store = unsafe { &mut NET_STORE };
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store.ip_addrs[0] = net::wire::IpCidr::new(net::wire::IpAddress::v4(10, 0, 16, 99), 24);
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let neighbor_cache = net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
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let interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
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.ethernet_addr(mac_addr)
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.neighbor_cache(neighbor_cache)
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.ip_addrs(&mut store.ip_addrs[..])
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.finalize();
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(interface, eth_mac)
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};
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cp.SCB.enable_icache();
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// Utilize the cycle counter for RTFM scheduling.
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cp.DWT.enable_cycle_counter();
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let mut dma = hal::dma::Dma::dma(dp.DMA1, dp.DMAMUX1, &clocks);
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dma.configure_m2p_stream(hal::dma::Stream::One,
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&SPI_START_CODE as *const _ as u32,
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&adc1_spi.spi.cr1 as *const _ as u32,
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hal::dma::DMAREQ_ID::TIM2_CH1);
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dma.configure_m2p_stream(hal::dma::Stream::Two,
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&SPI_START_CODE as *const _ as u32,
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&adc2_spi.spi.cr1 as *const _ as u32,
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hal::dma::DMAREQ_ID::TIM2_CH2);
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// Configure timer 2 to trigger conversions for the ADC
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let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
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timer2.configure_channel(hal::timer::Channel::One, 0.25);
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timer2.configure_channel(hal::timer::Channel::Two, 0.75);
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timer2.listen(hal::timer::Event::ChannelOneDma);
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timer2.listen(hal::timer::Event::ChannelTwoDma);
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init::LateResources {
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adc1: adc1_spi,
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dac1: dac1_spi,
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adc2: adc2_spi,
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dac2: dac2_spi,
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_afe1: afe1,
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_afe2: afe2,
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timer: timer2,
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//pounder: pounder_devices,
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eeprom_i2c: eeprom_i2c,
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net_interface: network_interface,
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_eth_mac: eth_mac,
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mac_addr: mac_addr,
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}
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}
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#[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch], priority = 2)]
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fn spi3(c: spi3::Context) {
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c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit());
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|
|
|
let output: u16 = {
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|
let a: u16 = c.resources.adc2.read().unwrap();
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|
let x0 = f32::from(a as i16);
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|
let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
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y0 as i16 as u16 ^ 0x8000
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};
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|
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c.resources.dac2.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit());
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c.resources.dac2.send(output).unwrap();
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}
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|
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#[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
|
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fn spi2(c: spi2::Context) {
|
|
c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
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|
|
|
let output: u16 = {
|
|
let a: u16 = c.resources.adc1.read().unwrap();
|
|
let x0 = f32::from(a as i16);
|
|
let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
|
|
y0 as i16 as u16 ^ 0x8000
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|
};
|
|
|
|
c.resources.dac1.spi.ifcr.write(|w| w.eotc().set_bit().txtfc().set_bit());
|
|
c.resources.dac1.send(output).unwrap();
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|
}
|
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|
|
#[idle(resources=[net_interface, mac_addr, iir_state, iir_ch])]
|
|
fn idle(mut c: idle::Context) -> ! {
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|
|
|
let mut socket_set_entries: [_; 8] = Default::default();
|
|
let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]);
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|
|
|
let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
|
|
let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
|
|
let tcp_handle0 = {
|
|
let tcp_rx_buffer = net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
|
|
let tcp_tx_buffer = net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
|
|
let tcp_socket = net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
|
|
sockets.add(tcp_socket)
|
|
};
|
|
|
|
let mut rx_storage2 = [0; TCP_RX_BUFFER_SIZE];
|
|
let mut tx_storage2 = [0; TCP_TX_BUFFER_SIZE];
|
|
let tcp_handle1 = {
|
|
let tcp_rx_buffer = net::socket::TcpSocketBuffer::new(&mut rx_storage2[..]);
|
|
let tcp_tx_buffer = net::socket::TcpSocketBuffer::new(&mut tx_storage2[..]);
|
|
let tcp_socket = net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
|
|
sockets.add(tcp_socket)
|
|
};
|
|
|
|
let mut server = server::Server::new();
|
|
|
|
let mut time = 0u32;
|
|
let mut next_ms = Instant::now();
|
|
|
|
// TODO: Replace with reference to CPU clock from CCDR.
|
|
next_ms += 400_000.cycles();
|
|
|
|
loop {
|
|
let tick = Instant::now() > next_ms;
|
|
|
|
if tick {
|
|
next_ms += 400_000.cycles();
|
|
time += 1;
|
|
}
|
|
|
|
{
|
|
let mut socket = sockets.get::<net::socket::TcpSocket>(tcp_handle0);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1234)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else if tick && socket.can_send() {
|
|
let s = c.resources.iir_state.lock(|iir_state| server::Status {
|
|
t: time,
|
|
x0: iir_state[0][0],
|
|
y0: iir_state[0][2],
|
|
x1: iir_state[1][0],
|
|
y1: iir_state[1][2],
|
|
});
|
|
server::json_reply(&mut socket, &s);
|
|
}
|
|
}
|
|
|
|
{
|
|
let socket =
|
|
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle1);
|
|
if socket.state() == net::socket::TcpState::CloseWait {
|
|
socket.close();
|
|
} else if !(socket.is_open() || socket.is_listening()) {
|
|
socket
|
|
.listen(1235)
|
|
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
|
|
} else {
|
|
server.poll(socket, |req: &server::Request| {
|
|
if req.channel < 2 {
|
|
c.resources.iir_ch.lock(|iir_ch| {
|
|
iir_ch[req.channel as usize] = req.iir
|
|
});
|
|
}
|
|
});
|
|
}
|
|
}
|
|
|
|
let sleep = match c.resources.net_interface.poll(&mut sockets,
|
|
net::time::Instant::from_millis(time as i64)) {
|
|
Ok(changed) => changed,
|
|
Err(net::Error::Unrecognized) => true,
|
|
Err(e) => {
|
|
info!("iface poll error: {:?}", e);
|
|
true
|
|
}
|
|
};
|
|
|
|
if sleep {
|
|
cortex_m::asm::wfi();
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
#[task(binds = ETH, resources = [net_interface], priority = 1)]
|
|
fn eth(c: eth::Context) {
|
|
let dma = &c.resources.net_interface.device();
|
|
ETHERNET_PENDING.store(true, Ordering::Relaxed);
|
|
dma.interrupt_handler()
|
|
}
|
|
*/
|
|
|
|
extern "C" {
|
|
// hw interrupt handlers for RTFM to use for scheduling tasks
|
|
// one per priority
|
|
fn DCMI();
|
|
fn JPEG();
|
|
fn SDMMC();
|
|
}
|
|
};
|
|
|
|
#[exception]
|
|
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
|
|
panic!("HardFault at {:#?}", ef);
|
|
}
|
|
|
|
#[exception]
|
|
fn DefaultHandler(irqn: i16) {
|
|
panic!("Unhandled exception (IRQn = {})", irqn);
|
|
}
|