65 lines
1.8 KiB
Rust
65 lines
1.8 KiB
Rust
use crate::hrtimer::HighResTimerE;
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use stm32h7xx_hal as hal;
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pub struct DdsOutput {
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profiles: heapless::spsc::Queue<[u32; 4], heapless::consts::U32>,
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update_timer: hal::timer::Timer<hal::stm32::TIM3>,
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io_update_trigger: HighResTimerE,
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}
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impl DdsOutput {
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pub fn new(
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mut timer: hal::timer::Timer<hal::stm32::TIM3>,
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io_update_trigger: HighResTimerE,
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) -> Self {
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timer.pause();
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timer.reset_counter();
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timer.clear_uif_bit();
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timer.listen(hal::timer::Event::TimeOut);
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Self {
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update_timer: timer,
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io_update_trigger,
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profiles: heapless::spsc::Queue::new(),
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}
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}
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pub fn update_handler(&mut self) {
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self.update_timer.clear_uif_bit();
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match self.profiles.dequeue() {
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Some(profile) => self.write_profile(profile),
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None => self.update_timer.pause(),
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}
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}
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pub fn push(&mut self, profile: [u32; 4]) {
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self.profiles.enqueue(profile).unwrap();
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self.update_timer.resume();
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}
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fn write_profile(&mut self, profile: [u32; 4]) {
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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unsafe {
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[0],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[1],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[2],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[3],
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);
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}
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// Trigger the IO_update signal generating timer to asynchronous create the IO_Update pulse.
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self.io_update_trigger.trigger();
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}
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}
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