pounder: qspi fifo is 32 deep
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@ -34,6 +34,7 @@ pub trait Interface {
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/// Indicates various communication modes of the DDS. The value of this enumeration is equivalent to
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/// Indicates various communication modes of the DDS. The value of this enumeration is equivalent to
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/// the configuration bits of the DDS CSR register.
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/// the configuration bits of the DDS CSR register.
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#[derive(Copy, Clone, PartialEq)]
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#[derive(Copy, Clone, PartialEq)]
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#[repr(u8)]
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pub enum Mode {
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pub enum Mode {
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SingleBitTwoWire = 0b00,
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SingleBitTwoWire = 0b00,
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SingleBitThreeWire = 0b01,
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SingleBitThreeWire = 0b01,
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@ -601,18 +602,13 @@ impl ProfileSerializer {
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#[inline]
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#[inline]
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fn pad(&mut self) {
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fn pad(&mut self) {
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// Pad the buffer to 32-bit (4 byte) alignment by adding dummy writes to CSR and LSRR.
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// Pad the buffer to 32-bit (4 byte) alignment by adding dummy writes to CSR and LSRR.
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match self.index & 3 {
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if self.index & 1 != 0 {
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3 => {
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self.add_write(Register::LSRR, &[0, 0]);
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// For a level of 3, we have to pad with 5 bytes to align things.
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self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
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self.add_write(Register::LSRR, &[0, 0]);
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}
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2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
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1 => self.add_write(Register::LSRR, &[0, 0]),
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0 => {}
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_ => unreachable!(),
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}
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}
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if self.index & 2 != 0 {
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self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
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}
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debug_assert_eq!(self.index & 3, 0);
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}
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}
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/// Get the serialized profile as a slice of 32-bit words.
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/// Get the serialized profile as a slice of 32-bit words.
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