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pounder: qspi fifo is 32 deep

This commit is contained in:
Robert Jördens 2021-08-02 15:00:27 +00:00
parent ffb7c8a5b0
commit e7ba24a7eb
1 changed files with 7 additions and 11 deletions
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18
ad9959/src/lib.rs
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@ -34,6 +34,7 @@ pub trait Interface {
/// Indicates various communication modes of the DDS. The value of this enumeration is equivalent to /// Indicates various communication modes of the DDS. The value of this enumeration is equivalent to
/// the configuration bits of the DDS CSR register. /// the configuration bits of the DDS CSR register.
#[derive(Copy, Clone, PartialEq)] #[derive(Copy, Clone, PartialEq)]
#[repr(u8)]
pub enum Mode { pub enum Mode {
SingleBitTwoWire = 0b00, SingleBitTwoWire = 0b00,
SingleBitThreeWire = 0b01, SingleBitThreeWire = 0b01,
@ -601,18 +602,13 @@ impl ProfileSerializer {
#[inline] #[inline]
fn pad(&mut self) { fn pad(&mut self) {
// Pad the buffer to 32-bit (4 byte) alignment by adding dummy writes to CSR and LSRR. // Pad the buffer to 32-bit (4 byte) alignment by adding dummy writes to CSR and LSRR.
match self.index & 3 { if self.index & 1 != 0 {
3 => { self.add_write(Register::LSRR, &[0, 0]);
// For a level of 3, we have to pad with 5 bytes to align things.
self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
self.add_write(Register::LSRR, &[0, 0]);
}
2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
1 => self.add_write(Register::LSRR, &[0, 0]),
0 => {}
_ => unreachable!(),
} }
if self.index & 2 != 0 {
self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
}
debug_assert_eq!(self.index & 3, 0);
} }
/// Get the serialized profile as a slice of 32-bit words. /// Get the serialized profile as a slice of 32-bit words.