move lock-in code to main.rs
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@ -116,7 +116,6 @@ where
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pub mod iir;
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pub mod iir;
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pub mod iir_int;
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pub mod iir_int;
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pub mod lockin;
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pub mod pll;
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pub mod pll;
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pub mod trig;
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pub mod trig;
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pub mod unwrap;
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pub mod unwrap;
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@ -1,392 +0,0 @@
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//! Lock-in amplifier.
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//!
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//! Lock-in processing is performed through a combination of the
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//! following modular processing blocks: demodulation, filtering,
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//! decimation and computing the magnitude and phase from a complex
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//! signal. These processing blocks are mutually independent.
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//!
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//! # Terminology
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//!
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//! * _demodulation signal_ - A copy of the reference signal that is
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//! optionally frequency scaled and phase shifted. This is a complex
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//! signal. The demodulation signals are used to demodulate the ADC
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//! sampled signal.
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//! * _internal clock_ - A fast internal clock used to increment a
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//! counter for determining the 0-phase points of a reference signal.
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//! * _reference signal_ - A constant-frequency signal used to derive
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//! the demodulation signal.
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//! * _timestamp_ - Timestamps record the timing of the reference
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//! signal's 0-phase points. For instance, if a reference signal is
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//! provided externally, a fast internal clock increments a
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//! counter. When the external reference reaches the 0-phase point
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//! (e.g., a positive edge), the value of the counter is recorded as a
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//! timestamp. These timestamps are used to determine the frequency
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//! and phase of the reference signal.
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//!
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//! # Usage
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//!
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//! The first step is to initialize a `Lockin` instance with
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//! `Lockin::new()`. This provides the lock-in algorithms with
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//! necessary information about the demodulation and filtering steps,
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//! such as whether to demodulate with a harmonic of the reference
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//! signal and the IIR biquad filter to use. There are then 4
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//! different processing steps that can be used:
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//!
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//! * `demodulate` - Computes the phase of the demodulation signal
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//! corresponding to each ADC sample, uses this phase to compute the
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//! demodulation signal, and multiplies this demodulation signal by
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//! the ADC-sampled signal. This is a method of `Lockin` since it
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//! requires information about how to modify the reference signal for
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//! demodulation.
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//! * `filter` - Performs IIR biquad filtering of a complex
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//! signals. This is commonly performed on the signal provided by the
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//! demodulation step, but can be performed at any other point in the
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//! processing chain or omitted entirely. `filter` is a method of
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//! `Lockin` since it must hold onto the filter configuration and
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//! state.
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//! * `decimate` - This decimates a signal to reduce the load on the
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//! DAC output. It does not require any state information and is
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//! therefore a normal function.
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//! * `magnitude_phase` - Computes the magnitude and phase of the
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//! component of the ADC-sampled signal whose frequency is equal to
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//! the demodulation frequency. This does not require any state
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//! information and is therefore a normal function.
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use super::iir_int::{IIRState, IIR};
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use super::pll::PLL;
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use super::trig::{atan2, cossin};
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use super::{divide_round, Complex};
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/// TODO these constants are copied from main.rs and should be
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/// shared. Additionally, we should probably store the log2 values and
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/// compute the actual values from these in main, as is done here.
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pub const SAMPLE_BUFFER_SIZE_LOG2: usize = 0;
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pub const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2;
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pub const ADC_SAMPLE_TICKS_LOG2: usize = 8;
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pub const ADC_SAMPLE_TICKS: usize = 1 << ADC_SAMPLE_TICKS_LOG2;
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pub const ADC_BATCHES_LOG2: usize =
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32 - SAMPLE_BUFFER_SIZE_LOG2 - ADC_SAMPLE_TICKS_LOG2;
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pub const ADC_BATCHES: usize = 1 << ADC_BATCHES_LOG2;
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pub const DECIMATED_BUFFER_SIZE: usize = 1;
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/// Performs lock-in amplifier processing of a signal.
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pub struct Lockin {
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harmonic: u32,
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phase_offset: u32,
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batch_index: u32,
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last_phase: Option<i64>,
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last_frequency: Option<i64>,
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pll: PLL,
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pll_shift_frequency: u8,
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pll_shift_phase: u8,
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iir: IIR,
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iirstate: [IIRState; 2],
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}
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impl Lockin {
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/// Initialize a new `Lockin` instance.
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///
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/// # Arguments
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///
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/// * `harmonic` - Integer scaling factor used to adjust the
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/// demodulation frequency. E.g., 2 would demodulate with the
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/// first harmonic.
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/// * `phase_offset` - Phase offset applied to the demodulation
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/// signal.
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/// * `iir` - IIR biquad filter.
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/// * `pll_shift_frequency` - See PLL::update().
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/// * `pll_shift_phase` - See PLL::update().
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///
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/// # Returns
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///
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/// New `Lockin` instance.
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pub fn new(
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harmonic: u32,
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phase_offset: u32,
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iir: IIR,
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pll_shift_frequency: u8,
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pll_shift_phase: u8,
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) -> Self {
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Lockin {
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harmonic,
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phase_offset,
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batch_index: 0,
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last_phase: None,
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last_frequency: None,
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pll: PLL::default(),
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pll_shift_frequency,
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pll_shift_phase,
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iir,
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iirstate: [[0; 5]; 2],
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}
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}
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/// Demodulate an input signal with the complex reference signal.
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///
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/// # Arguments
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///
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/// * `adc_samples` - One batch of ADC samples.
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/// * `timestamp` - Counter value corresponding to the edges of an
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/// external reference signal. The counter is incremented by a
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/// fast internal clock. Each ADC sample batch can contain 0 or 1
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/// timestamps.
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///
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/// # Returns
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///
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/// The demodulated complex signal as a `Result`. When there are
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/// an insufficient number of timestamps to perform processing,
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/// `Err` is returned.
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pub fn demodulate(
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&mut self,
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adc_samples: &[i16],
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timestamp: Option<u32>,
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) -> Result<[Complex<i32>; SAMPLE_BUFFER_SIZE], &str> {
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let frequency: i64;
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let phase: i64;
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match timestamp {
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Some(t) => {
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let res = self.pll.update(
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t as i32,
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self.pll_shift_frequency,
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self.pll_shift_phase,
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);
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phase = res.0 as u32 as i64;
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frequency = res.1 as u32 as i64;
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self.last_phase = Some(phase);
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self.last_frequency = Some(frequency);
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}
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None => match self.last_phase {
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Some(t) => {
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phase = t;
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frequency = self.last_frequency.unwrap();
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}
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None => {
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if self.batch_index < ADC_BATCHES as u32 - 1 {
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self.batch_index += 1;
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} else {
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self.batch_index = 0;
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}
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return Err("insufficient timestamps");
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}
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},
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}
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let demodulation_frequency = divide_round(
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1 << (64 - SAMPLE_BUFFER_SIZE_LOG2 - ADC_BATCHES_LOG2),
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frequency,
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) as u32;
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let demodulation_initial_phase = divide_round(
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(((self.batch_index as i64) << (32 - ADC_BATCHES_LOG2)) - phase)
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<< 32,
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frequency,
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) as u32;
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let mut demodulation_signal = [(0_i32, 0_i32); SAMPLE_BUFFER_SIZE];
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demodulation_signal
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.iter_mut()
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.zip(adc_samples.iter())
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.enumerate()
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.for_each(|(i, (s, sample))| {
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let sample_phase = (self.harmonic.wrapping_mul(
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(demodulation_frequency.wrapping_mul(i as u32))
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.wrapping_add(demodulation_initial_phase),
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))
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.wrapping_add(self.phase_offset);
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let (cos, sin) = cossin(sample_phase as i32);
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// cos/sin take up 32 bits and sample takes up 16
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// bits. Make this fit into a 32 bit result.
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s.0 = ((*sample as i64 * cos as i64) >> 16) as i32;
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s.1 = ((*sample as i64 * sin as i64) >> 16) as i32;
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});
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if self.batch_index < ADC_BATCHES as u32 - 1 {
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self.batch_index += 1;
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} else {
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self.batch_index = 0;
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self.last_phase = Some(self.last_phase.unwrap() - (1 << 32));
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}
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Ok(demodulation_signal)
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}
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/// Filter the complex signal using the supplied biquad IIR. The
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/// signal array is modified in place.
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///
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/// # Arguments
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///
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/// * `signal` - Complex signal to filter.
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pub fn filter(&mut self, signal: &mut [Complex<i32>]) {
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signal.iter_mut().for_each(|s| {
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s.0 = self.iir.update(&mut self.iirstate[0], s.0);
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s.1 = self.iir.update(&mut self.iirstate[1], s.1);
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});
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}
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}
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/// Decimate the complex signal to `DECIMATED_BUFFER_SIZE`. The ratio
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/// of `SAMPLE_BUFFER_SIZE` to `DECIMATED_BUFFER_SIZE` must be a power
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/// of 2.
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///
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/// # Arguments
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///
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/// * `signal` - Complex signal to decimate.
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///
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/// # Returns
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///
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/// The decimated signal.
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pub fn decimate(
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signal: [Complex<i32>; SAMPLE_BUFFER_SIZE],
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) -> [Complex<i32>; DECIMATED_BUFFER_SIZE] {
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let n_k = SAMPLE_BUFFER_SIZE / DECIMATED_BUFFER_SIZE;
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debug_assert!(SAMPLE_BUFFER_SIZE == DECIMATED_BUFFER_SIZE || n_k % 2 == 0);
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let mut signal_decimated = [(0_i32, 0_i32); DECIMATED_BUFFER_SIZE];
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signal_decimated
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.iter_mut()
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.zip(signal.iter().step_by(n_k))
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.for_each(|(s_d, s)| {
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s_d.0 = s.0;
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s_d.1 = s.1;
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});
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signal_decimated
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}
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/// Compute the magnitude and phase from the complex signal. The
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/// signal array is modified in place.
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///
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/// # Arguments
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///
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/// * `signal` - Complex signal for which the magnitude and phase
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/// should be computed. TODO currently, we compute the square of the
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/// magnitude. This should be changed to be the actual magnitude.
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pub fn magnitude_phase(signal: &mut [Complex<i32>]) {
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signal.iter_mut().for_each(|s| {
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let new_i = [s.0, s.1].iter().map(|i| i * i).sum();
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let new_q = atan2(s.1, s.0);
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s.0 = new_i;
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s.1 = new_q;
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});
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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/// Ensure that the demodulation signals are within some tolerance
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/// band of the target value given the phase and frequency values
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/// provided by the PLL.
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fn demodulate() {
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const PLL_SHIFT_FREQUENCY: u8 = 4;
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const PLL_SHIFT_PHASE: u8 = 3;
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const HARMONIC: u32 = 1;
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const PHASE_OFFSET: u32 = 0;
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let mut lockin = Lockin::new(
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HARMONIC,
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PHASE_OFFSET,
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IIR { ba: [0; 5] },
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PLL_SHIFT_FREQUENCY,
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PLL_SHIFT_PHASE,
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);
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// Duplicate the PLL outside demodulate so that we don't test
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// its behavior.
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let mut tracking_pll = PLL::default();
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let mut tracking_phase: i32 = 0;
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let mut tracking_frequency: i32 = 0;
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const REFERENCE_FREQUENCY: usize = 10_000;
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let mut reference_edge: usize = REFERENCE_FREQUENCY;
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// Ensure that we receive at most 1 timestamp per batch.
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debug_assert!(
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REFERENCE_FREQUENCY >= SAMPLE_BUFFER_SIZE * ADC_SAMPLE_TICKS
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);
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for batch in 0..100_000 {
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let tick: usize = batch * ADC_SAMPLE_TICKS * SAMPLE_BUFFER_SIZE;
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let timestamp: Option<u32>;
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// When the reference edge occurred during the current
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// batch acquisition, register the timestamp and update
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// the tracking PLL.
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if reference_edge >= tick
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&& reference_edge < tick + ADC_SAMPLE_TICKS * SAMPLE_BUFFER_SIZE
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{
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timestamp = Some(reference_edge as u32);
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let tracking_update = tracking_pll.update(
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reference_edge as i32,
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PLL_SHIFT_FREQUENCY,
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PLL_SHIFT_PHASE,
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);
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tracking_phase = tracking_update.0;
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tracking_frequency = tracking_update.1;
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reference_edge += REFERENCE_FREQUENCY;
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} else {
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timestamp = None;
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}
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let timestamp_before_batch = if tracking_phase > tick as i32 {
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// There can be at most 1 reference edge per batch, so
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// this will necessarily place the timestamp prior to
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// the current batch.
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tracking_phase - tracking_frequency
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} else {
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tracking_phase
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};
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let initial_phase = (((tick as f64
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- timestamp_before_batch as f64)
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/ tracking_frequency as f64
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* (1_i64 << 32) as f64)
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.round()
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% u32::MAX as f64) as u32;
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let frequency = ((ADC_SAMPLE_TICKS as f64
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/ tracking_frequency as f64
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* (1_i64 << 32) as f64)
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.round()
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% u32::MAX as f64) as u32;
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match lockin.demodulate(&[i16::MAX; SAMPLE_BUFFER_SIZE], timestamp)
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{
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Ok(v) => {
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println!("batch : {}", batch);
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for sample in 0..SAMPLE_BUFFER_SIZE {
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const TOL: i32 = 50_000;
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let cos = v[sample].0;
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let sin = v[sample].1;
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let (mut target_cos, mut target_sin) = cossin(
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HARMONIC
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.wrapping_mul(
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(frequency.wrapping_mul(sample as u32))
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||||||
.wrapping_add(initial_phase),
|
|
||||||
)
|
|
||||||
.wrapping_add(PHASE_OFFSET)
|
|
||||||
as i32,
|
|
||||||
);
|
|
||||||
target_cos /= 2;
|
|
||||||
target_sin /= 2;
|
|
||||||
|
|
||||||
println!("sample : {}", sample);
|
|
||||||
println!("tol : {}", TOL);
|
|
||||||
println!("cos, target: {}, {}", cos, target_cos);
|
|
||||||
println!("sin, target: {}, {}", sin, target_sin);
|
|
||||||
assert!((cos - target_cos).abs() < TOL);
|
|
||||||
assert!((sin - target_sin).abs() < TOL);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Err(_) => {}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
130
src/main.rs
130
src/main.rs
@ -60,14 +60,34 @@ use heapless::{consts::*, String};
|
|||||||
// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
|
// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
|
||||||
// equal to 10ns per tick.
|
// equal to 10ns per tick.
|
||||||
// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
|
// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
|
||||||
const ADC_SAMPLE_TICKS: u16 = 256;
|
const ADC_SAMPLE_TICKS_LOG2: u16 = 8;
|
||||||
|
const ADC_SAMPLE_TICKS: u16 = 1 << ADC_SAMPLE_TICKS_LOG2;
|
||||||
|
|
||||||
// The desired ADC sample processing buffer size.
|
// The desired ADC sample processing buffer size.
|
||||||
const SAMPLE_BUFFER_SIZE: usize = 8;
|
const SAMPLE_BUFFER_SIZE_LOG2: usize = 3;
|
||||||
|
const SAMPLE_BUFFER_SIZE: usize = 1 << SAMPLE_BUFFER_SIZE_LOG2;
|
||||||
|
|
||||||
|
// The number of ADC batches in one timer overflow period.
|
||||||
|
pub const ADC_BATCHES_LOG2: usize =
|
||||||
|
32 - SAMPLE_BUFFER_SIZE_LOG2 - ADC_SAMPLE_TICKS_LOG2 as usize;
|
||||||
|
pub const ADC_BATCHES: usize = 1 << ADC_BATCHES_LOG2;
|
||||||
|
|
||||||
// The number of cascaded IIR biquads per channel. Select 1 or 2!
|
// The number of cascaded IIR biquads per channel. Select 1 or 2!
|
||||||
const IIR_CASCADE_LENGTH: usize = 1;
|
const IIR_CASCADE_LENGTH: usize = 1;
|
||||||
|
|
||||||
|
// TODO should these be global consts?
|
||||||
|
|
||||||
|
// Frequency scaling factor for lock-in harmonic demodulation.
|
||||||
|
const HARMONIC: u32 = 1;
|
||||||
|
|
||||||
|
// Phase offset applied to the lock-in demodulation signal.
|
||||||
|
const PHASE_OFFSET: u32 = 0;
|
||||||
|
|
||||||
|
// The PLL locks to an external reference signal. See `PLL::update()`
|
||||||
|
// for a description of shift_frequency and shift_phase.
|
||||||
|
const PLL_SHIFT_FREQUENCY: u8 = 4;
|
||||||
|
const PLL_SHIFT_PHASE: u8 = 3;
|
||||||
|
|
||||||
#[link_section = ".sram3.eth"]
|
#[link_section = ".sram3.eth"]
|
||||||
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
|
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
|
||||||
|
|
||||||
@ -84,7 +104,11 @@ mod timers;
|
|||||||
|
|
||||||
use adc::{Adc0Input, Adc1Input};
|
use adc::{Adc0Input, Adc1Input};
|
||||||
use dac::{Dac0Output, Dac1Output};
|
use dac::{Dac0Output, Dac1Output};
|
||||||
use dsp::iir;
|
use dsp::{
|
||||||
|
divide_round, iir, iir_int,
|
||||||
|
pll::PLL,
|
||||||
|
trig::{atan2, cossin},
|
||||||
|
};
|
||||||
use pounder::DdsOutput;
|
use pounder::DdsOutput;
|
||||||
|
|
||||||
#[cfg(not(feature = "semihosting"))]
|
#[cfg(not(feature = "semihosting"))]
|
||||||
@ -205,6 +229,12 @@ const APP: () = {
|
|||||||
adcs: (Adc0Input, Adc1Input),
|
adcs: (Adc0Input, Adc1Input),
|
||||||
dacs: (Dac0Output, Dac1Output),
|
dacs: (Dac0Output, Dac1Output),
|
||||||
input_stamper: digital_input_stamper::InputStamper,
|
input_stamper: digital_input_stamper::InputStamper,
|
||||||
|
pll: PLL,
|
||||||
|
batch_index: u32,
|
||||||
|
reference_phase: i64,
|
||||||
|
reference_frequency: i64,
|
||||||
|
iir_lockin: iir_int::IIR,
|
||||||
|
iir_state_lockin: [iir_int::IIRState; 2],
|
||||||
|
|
||||||
eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
|
eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
|
||||||
|
|
||||||
@ -927,6 +957,13 @@ const APP: () = {
|
|||||||
#[cfg(not(feature = "pounder_v1_1"))]
|
#[cfg(not(feature = "pounder_v1_1"))]
|
||||||
let pounder_stamper = None;
|
let pounder_stamper = None;
|
||||||
|
|
||||||
|
let pll = PLL::default();
|
||||||
|
let batch_index = 0;
|
||||||
|
let reference_phase = 0;
|
||||||
|
let reference_frequency = 0;
|
||||||
|
let iir_lockin = iir_int::IIR { ba: [0; 5] };
|
||||||
|
let iir_state_lockin = [[0; 5]; 2];
|
||||||
|
|
||||||
// Start sampling ADCs.
|
// Start sampling ADCs.
|
||||||
sampling_timer.start();
|
sampling_timer.start();
|
||||||
timestamp_timer.start();
|
timestamp_timer.start();
|
||||||
@ -942,6 +979,13 @@ const APP: () = {
|
|||||||
pounder: pounder_devices,
|
pounder: pounder_devices,
|
||||||
pounder_stamper,
|
pounder_stamper,
|
||||||
|
|
||||||
|
pll,
|
||||||
|
batch_index,
|
||||||
|
reference_phase,
|
||||||
|
reference_frequency,
|
||||||
|
iir_lockin,
|
||||||
|
iir_state_lockin,
|
||||||
|
|
||||||
eeprom_i2c,
|
eeprom_i2c,
|
||||||
net_interface: network_interface,
|
net_interface: network_interface,
|
||||||
eth_mac,
|
eth_mac,
|
||||||
@ -949,7 +993,7 @@ const APP: () = {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[task(binds=DMA1_STR4, resources=[pounder_stamper, adcs, dacs, iir_state, iir_ch, dds_output, input_stamper], priority=2)]
|
#[task(binds=DMA1_STR4, resources=[pounder_stamper, adcs, dacs, iir_state, iir_ch, dds_output, input_stamper, pll, iir_lockin, iir_state_lockin, batch_index, reference_phase, reference_frequency], priority=2)]
|
||||||
fn process(c: process::Context) {
|
fn process(c: process::Context) {
|
||||||
if let Some(stamper) = c.resources.pounder_stamper {
|
if let Some(stamper) = c.resources.pounder_stamper {
|
||||||
let pounder_timestamps = stamper.acquire_buffer();
|
let pounder_timestamps = stamper.acquire_buffer();
|
||||||
@ -965,24 +1009,71 @@ const APP: () = {
|
|||||||
c.resources.dacs.1.acquire_buffer(),
|
c.resources.dacs.1.acquire_buffer(),
|
||||||
];
|
];
|
||||||
|
|
||||||
let _timestamp = c.resources.input_stamper.latest_timestamp();
|
let reference_phase = c.resources.reference_phase;
|
||||||
|
let reference_frequency = c.resources.reference_frequency;
|
||||||
|
|
||||||
for channel in 0..adc_samples.len() {
|
if let Some(t) = c.resources.input_stamper.latest_timestamp() {
|
||||||
for sample in 0..adc_samples[0].len() {
|
let res = c.resources.pll.update(
|
||||||
let x = f32::from(adc_samples[channel][sample] as i16);
|
t as i32,
|
||||||
let mut y = x;
|
PLL_SHIFT_FREQUENCY,
|
||||||
for i in 0..c.resources.iir_state[channel].len() {
|
PLL_SHIFT_PHASE,
|
||||||
y = c.resources.iir_ch[channel][i]
|
);
|
||||||
.update(&mut c.resources.iir_state[channel][i], y);
|
*reference_phase = res.0 as u32 as i64;
|
||||||
}
|
*reference_frequency = res.1 as u32 as i64;
|
||||||
// Note(unsafe): The filter limits ensure that the value is in range.
|
|
||||||
// The truncation introduces 1/2 LSB distortion.
|
|
||||||
let y = unsafe { y.to_int_unchecked::<i16>() };
|
|
||||||
// Convert to DAC code
|
|
||||||
dac_samples[channel][sample] = y as u16 ^ 0x8000;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
let demodulation_frequency = divide_round(
|
||||||
|
1 << (64 - SAMPLE_BUFFER_SIZE_LOG2 - ADC_BATCHES_LOG2),
|
||||||
|
*reference_frequency,
|
||||||
|
) as u32;
|
||||||
|
let batch_index = c.resources.batch_index;
|
||||||
|
let demodulation_initial_phase = divide_round(
|
||||||
|
(((*batch_index as i64) << (32 - ADC_BATCHES_LOG2))
|
||||||
|
- *reference_phase)
|
||||||
|
<< 32,
|
||||||
|
*reference_frequency,
|
||||||
|
) as u32;
|
||||||
|
|
||||||
|
if *batch_index < ADC_BATCHES as u32 - 1 {
|
||||||
|
*batch_index += 1;
|
||||||
|
} else {
|
||||||
|
*batch_index = 0;
|
||||||
|
*reference_phase -= 1 << 32;
|
||||||
|
}
|
||||||
|
|
||||||
|
let [dac0, dac1] = dac_samples;
|
||||||
|
let iir_lockin = c.resources.iir_lockin;
|
||||||
|
let iir_state_lockin = c.resources.iir_state_lockin;
|
||||||
|
|
||||||
|
dac0.iter_mut().zip(dac1.iter_mut()).enumerate().for_each(
|
||||||
|
|(i, (d0, d1))| {
|
||||||
|
let sample_phase = (HARMONIC.wrapping_mul(
|
||||||
|
(demodulation_frequency.wrapping_mul(i as u32))
|
||||||
|
.wrapping_add(demodulation_initial_phase),
|
||||||
|
))
|
||||||
|
.wrapping_add(PHASE_OFFSET);
|
||||||
|
let (cos, sin) = cossin(sample_phase as i32);
|
||||||
|
|
||||||
|
let mut signal = (0_i32, 0_i32);
|
||||||
|
|
||||||
|
signal.0 = ((adc_samples[0][i] as i16 as i64 * cos as i64)
|
||||||
|
>> 16) as i32;
|
||||||
|
signal.1 = ((adc_samples[0][i] as i16 as i64 * sin as i64)
|
||||||
|
>> 16) as i32;
|
||||||
|
|
||||||
|
signal.0 =
|
||||||
|
iir_lockin.update(&mut iir_state_lockin[0], signal.0);
|
||||||
|
signal.1 =
|
||||||
|
iir_lockin.update(&mut iir_state_lockin[1], signal.0);
|
||||||
|
|
||||||
|
let magnitude = signal.0 * signal.0 + signal.1 * signal.1;
|
||||||
|
let phase = atan2(signal.0, signal.0);
|
||||||
|
|
||||||
|
*d0 = (magnitude >> 16) as i16 as u16;
|
||||||
|
*d1 = (phase >> 16) as i16 as u16;
|
||||||
|
},
|
||||||
|
);
|
||||||
|
|
||||||
if let Some(dds_output) = c.resources.dds_output {
|
if let Some(dds_output) = c.resources.dds_output {
|
||||||
let builder = dds_output.builder().update_channels(
|
let builder = dds_output.builder().update_channels(
|
||||||
&[pounder::Channel::Out0.into()],
|
&[pounder::Channel::Out0.into()],
|
||||||
@ -994,7 +1085,6 @@ const APP: () = {
|
|||||||
builder.write_profile();
|
builder.write_profile();
|
||||||
}
|
}
|
||||||
|
|
||||||
let [dac0, dac1] = dac_samples;
|
|
||||||
c.resources.dacs.0.release_buffer(dac0);
|
c.resources.dacs.0.release_buffer(dac0);
|
||||||
c.resources.dacs.1.release_buffer(dac1);
|
c.resources.dacs.1.release_buffer(dac1);
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user