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pounder_test
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back to tsize=1 adc

master
Robert Jördens 2019-03-20 19:28:23 +00:00
parent a2265ab2d1
commit aa3feeb14e
1 changed files with 9 additions and 11 deletions
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20
src/main.rs
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@ -286,13 +286,13 @@ fn spi1_setup(spi1: &stm32::SPI1) {
.lsbfrst().clear_bit() .lsbfrst().clear_bit()
.master().set_bit() .master().set_bit()
.sp().bits(0) // motorola .sp().bits(0) // motorola
.comm().bits(0b00) // duplex .comm().bits(0b10) // simplex receiver
.ioswp().clear_bit() .ioswp().clear_bit()
.midi().bits(0) // master inter data idle .midi().bits(0) // master inter data idle
.mssi().bits(11) // master SS idle .mssi().bits(11) // master SS idle
}); });
spi1.cr2.modify(|_, w| unsafe { spi1.cr2.modify(|_, w| unsafe {
w.tsize().bits(0) w.tsize().bits(1)
}); });
spi1.cr1.write(|w| w.spe().set_bit()); spi1.cr1.write(|w| w.spe().set_bit());
} }
@ -366,13 +366,10 @@ fn main() -> ! {
let spi2 = dp.SPI2; let spi2 = dp.SPI2;
spi2_setup(&spi2); spi2_setup(&spi2);
// at least one SCK between EOT and CSTART
spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
// at least one SCK between EOT and CSTART // at least one SCK between EOT and CSTART
spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
// needs to be a half word write // needs to be a half word write
let txdr1 = &spi1.txdr as *const _ as *mut u16;
let rxdr1 = &spi1.rxdr as *const _ as *const u16; let rxdr1 = &spi1.rxdr as *const _ as *const u16;
// needs to be a half word write // needs to be a half word write
let txdr2 = &spi2.txdr as *const _ as *mut u16; let txdr2 = &spi2.txdr as *const _ as *mut u16;
@ -380,14 +377,15 @@ fn main() -> ! {
#[cfg(feature = "bkpt")] #[cfg(feature = "bkpt")]
cortex_m::asm::bkpt(); cortex_m::asm::bkpt();
while spi1.sr.read().txp().bit_is_clear() {} // at least one SCK between EOT and CSTART
unsafe { ptr::write_volatile(txdr1, 0) }; spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
// while spi1.sr.read().txc().bit_is_clear() {} while spi1.sr.read().eot().bit_is_clear() {}
while spi1.sr.read().rxp().bit_is_clear() {} spi1.ifcr.write(|w| w.eotc().set_bit());
// while spi1.sr.read().rxp().bit_is_clear() {}
let a = unsafe { ptr::read_volatile(rxdr1) }; let a = unsafe { ptr::read_volatile(rxdr1) };
while spi2.sr.read().txp().bit_is_clear() {} // while spi2.sr.read().txp().bit_is_clear() {}
unsafe { ptr::write_volatile(txdr2, a ^ 0x8000) }; unsafe { ptr::write_volatile(txdr2, a ^ 0x8000) };
// while spi2.sr.read().txc().bit_is_clear() {} while spi2.sr.read().txc().bit_is_clear() {}
#[cfg(feature = "bkpt")] #[cfg(feature = "bkpt")]
cortex_m::asm::bkpt(); cortex_m::asm::bkpt();