lowpass: expose natural gain, add bias

master
Robert Jördens 2021-02-12 11:06:59 +01:00
parent 67f052c0c9
commit a6d4099ed3
2 changed files with 8 additions and 8 deletions

View File

@ -14,21 +14,21 @@ impl<N: ArrayLength<i32>> Lowpass<N> {
/// Update the filter with a new sample. /// Update the filter with a new sample.
/// ///
/// # Args /// # Args
/// * `x`: Input data /// * `x`: Input data, needs `k` bits headroom.
/// * `k`: Log2 time constant, 0..31 /// * `k`: Log2 time constant, 0..31.
/// ///
/// # Return /// # Return
/// Filtered output y, needs `k` bits headroom /// Filtered output y, with gain of `1 << k`.
pub fn update(&mut self, x: i32, k: u8) -> i32 { pub fn update(&mut self, x: i32, k: u8) -> i32 {
debug_assert!(k & 31 == k); debug_assert!(k & 31 == k);
// This is an unrolled and optimized first-order IIR loop // This is an unrolled and optimized first-order IIR loop
// that works for all possible time constants. // that works for all possible time constants.
// Note DF-II and the zeros at Nyquist. // Note DF-II and the zeros at Nyquist.
let mut x = x; let mut x = x << k;
for y in self.y.iter_mut() { for y in self.y.iter_mut() {
let dy = x - (*y >> k); let dy = (x - *y + (1 << (k - 1))) >> k;
*y += dy; *y += dy;
x = (*y - (dy >> 1)) >> k; x = *y - (dy >> 1);
} }
x x
} }

View File

@ -103,7 +103,7 @@ const APP: () = {
let phase_offset: i32 = 0; // TODO: expose let phase_offset: i32 = 0; // TODO: expose
// Log2 lowpass time constant // Log2 lowpass time constant
let time_constant: u8 = 8; // TODO: expose let time_constant: u8 = 6; // TODO: expose
let sample_frequency = ((pll_frequency let sample_frequency = ((pll_frequency
// .wrapping_add(1 << design_parameters::SAMPLE_BUFFER_SIZE_LOG2 - 1) // half-up rounding bias // .wrapping_add(1 << design_parameters::SAMPLE_BUFFER_SIZE_LOG2 - 1) // half-up rounding bias
@ -128,7 +128,7 @@ const APP: () = {
// Convert from IQ to power and phase. // Convert from IQ to power and phase.
"power_phase" => [(output.log2() << 24) as _, output.arg()], "power_phase" => [(output.log2() << 24) as _, output.arg()],
"frequency_discriminator" => [pll_frequency as _, output.arg()], "frequency_discriminator" => [pll_frequency as _, output.arg()],
_ => [output.0 << 16, output.1 << 16], _ => [output.0, output.1],
}; };
// Convert to DAC data. // Convert to DAC data.