work around erratum 2.10.2

src/main.rs

@@ -141,8 +141,8 @@ fn main() -> ! {
     rcc.cr.modify(|_, w| w.pll2on().set_bit());
     while rcc.cr.read().pll2rdy().bit_is_clear() {}
 
-    // hclk 200 MHz, pclk 100 MHz
-    let dapb = 0b100;
+    // hclk 200 MHz, pclk 50 MHz
+    let dapb = 0b101;
     rcc.d1cfgr.write(|w| unsafe {
         w.d1cpre().bits(0)  // sys_ck not divided
          .hpre().bits(0b1000)  // rcc_hclk3 = sys_d1cpre_ck / 2
@@ -268,7 +268,7 @@ fn main() -> ! {
     let spi1 = dp.SPI1;
     spi1.cfg1.modify(|_, w| unsafe {
         // w.mbr().bits(0)  // clk/2
-        w.mbr().bits(1)  // FIXME
+        w.mbr().bits(0)  // FIXME
          .dsize().bits(16 - 1)
          .fthvl().bits(1 - 1)  // one data
     });