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stm32h7 svd and pac changes

This commit is contained in:
Robert Jördens 2019-05-06 08:48:22 +00:00
parent 61adbd8c9e
commit 86dbdf98e2
2 changed files with 7 additions and 11 deletions
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16
src/eth.rs
View File

@ -360,7 +360,6 @@ impl Device {
cortex_m::interrupt::free(|_cs| { cortex_m::interrupt::free(|_cs| {
let eth_mac = &*stm32::ETHERNET_MAC::ptr(); let eth_mac = &*stm32::ETHERNET_MAC::ptr();
let eth_dma = &*stm32::ETHERNET_DMA::ptr(); let eth_dma = &*stm32::ETHERNET_DMA::ptr();
let _eth_mmc = &*stm32::ETHERNET_MMC::ptr();
let eth_mtl = &*stm32::ETHERNET_MTL::ptr(); let eth_mtl = &*stm32::ETHERNET_MTL::ptr();
eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
@ -407,9 +406,6 @@ impl Device {
eth_mac.maca0hr.write(|w| eth_mac.maca0hr.write(|w|
w.addrhi().bits( u16::from(mac.0[4]) | w.addrhi().bits( u16::from(mac.0[4]) |
(u16::from(mac.0[5]) << 8)) (u16::from(mac.0[5]) << 8))
.ae().set_bit()
//.sa().clear_bit()
//.mbc().bits(0b000000)
); );
// frame filter register // frame filter register
eth_mac.macpfr.modify(|_, w| { eth_mac.macpfr.modify(|_, w| {
@ -433,12 +429,12 @@ impl Device {
}); });
eth_mac.macwtr.write(|w| w.pwe().clear_bit()); eth_mac.macwtr.write(|w| w.pwe().clear_bit());
// Flow Control Register // Flow Control Register
eth_mac.macqtxfcr.modify(|_, w| { eth_mac.macqtx_fcr.modify(|_, w| {
// Pause time // Pause time
w.pt().bits(0x100) w.pt().bits(0x100)
}); });
eth_mac.macrxfcr.modify(|_, w| w); eth_mac.macrx_fcr.modify(|_, w| w);
eth_mtl.mtlrxqomr.modify(|_, w| eth_mtl.mtlrx_qomr.modify(|_, w|
w w
// Receive store and forward // Receive store and forward
.rsf().set_bit() .rsf().set_bit()
@ -449,7 +445,7 @@ impl Device {
// Forward undersized good packets // Forward undersized good packets
.fup().clear_bit() .fup().clear_bit()
); );
eth_mtl.mtltxqomr.modify(|_, w| { eth_mtl.mtltx_qomr.modify(|_, w| {
w w
// Transmit store and forward // Transmit store and forward
.tsf().set_bit() .tsf().set_bit()
@ -473,7 +469,7 @@ impl Device {
// operation mode register // operation mode register
eth_dma.dmamr.modify(|_, w| { eth_dma.dmamr.modify(|_, w| {
w w
.intm().clear_bit() // FIXME: bits(0b00) .intm().bits(0b00)
// Rx Tx priority ratio 1:1 // Rx Tx priority ratio 1:1
.pr().bits(0b000) .pr().bits(0b000)
.txpr().clear_bit() .txpr().clear_bit()
@ -519,7 +515,7 @@ impl Device {
w.re().bit(true) // Receiver Enable w.re().bit(true) // Receiver Enable
.te().bit(true) // Transmiter Enable .te().bit(true) // Transmiter Enable
}); });
eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit()); eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
// Manage DMA transmission and reception // Manage DMA transmission and reception
eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());

2
src/main.rs
View File

@ -56,7 +56,7 @@ mod build_info {
fn pwr_setup(pwr: &stm32::PWR) { fn pwr_setup(pwr: &stm32::PWR) {
// go to VOS1 voltage scale for high perf // go to VOS1 voltage scale for high perf
pwr.cr3.write(|w| pwr.cr3.write(|w|
w.sden().set_bit() w.scuen().set_bit()
.ldoen().set_bit() .ldoen().set_bit()
.bypass().clear_bit() .bypass().clear_bit()
); );