use rtfm [wip]

This commit is contained in:
Robert Jördens 2019-05-30 16:03:48 +00:00
parent f0ec1e37fc
commit 7501ea1963
3 changed files with 271 additions and 184 deletions

62
Cargo.lock generated
View File

@ -1,5 +1,10 @@
# This file is automatically @generated by Cargo. # This file is automatically @generated by Cargo.
# It is not intended for manual editing. # It is not intended for manual editing.
[[package]]
name = "aligned"
version = "0.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]] [[package]]
name = "aligned" name = "aligned"
version = "0.3.1" version = "0.3.1"
@ -40,6 +45,17 @@ name = "cfg-if"
version = "0.1.9" version = "0.1.9"
source = "registry+https://github.com/rust-lang/crates.io-index" source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]]
name = "cortex-m"
version = "0.5.10"
source = "registry+https://github.com/rust-lang/crates.io-index"
dependencies = [
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"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]] [[package]]
name = "cortex-m" name = "cortex-m"
version = "0.6.0" version = "0.6.0"
@ -80,6 +96,27 @@ dependencies = [
"syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)",
] ]
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version = "0.5.0-alpha.1"
source = "git+https://github.com/japaric/cortex-m-rtfm#fafeeb27270ef24fc3852711c6032f65aa7dbcc0"
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[[package]] [[package]]
name = "cortex-m-semihosting" name = "cortex-m-semihosting"
version = "0.3.3" version = "0.3.3"
@ -104,6 +141,14 @@ dependencies = [
"typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
] ]
[[package]]
name = "generic-array"
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source = "registry+https://github.com/rust-lang/crates.io-index"
dependencies = [
"typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]] [[package]]
name = "hash32" name = "hash32"
version = "0.1.0" version = "0.1.0"
@ -122,6 +167,16 @@ dependencies = [
"hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
] ]
[[package]]
name = "heapless"
version = "0.5.0-alpha.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
dependencies = [
"as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
"generic-array 0.13.0 (registry+https://github.com/rust-lang/crates.io-index)",
"hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]] [[package]]
name = "log" name = "log"
version = "0.4.6" version = "0.4.6"
@ -256,6 +311,7 @@ dependencies = [
"cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
"cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)",
"cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)",
"cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)",
"heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)",
"log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)",
"panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)",
@ -315,21 +371,27 @@ dependencies = [
] ]
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View File

@ -53,6 +53,10 @@ version = "0.5"
features = ["proto-ipv4", "socket-tcp"] features = ["proto-ipv4", "socket-tcp"]
default-features = false default-features = false
[dependencies.cortex-m-rtfm]
git = "https://github.com/japaric/cortex-m-rtfm"
features = ["timer-queue"]
[features] [features]
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
bkpt = [ ] bkpt = [ ]

View File

@ -13,12 +13,10 @@ extern crate panic_semihosting;
extern crate log; extern crate log;
use core::ptr; use core::ptr;
use core::cell::RefCell;
use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
use core::fmt::Write; use core::fmt::Write;
use cortex_m_rt::{entry, exception}; use cortex_m_rt::{exception};
use stm32h7::stm32h7x3::{self as stm32, Peripherals, CorePeripherals, interrupt}; use stm32h7::stm32h7x3::{self as stm32, interrupt};
use cortex_m::interrupt::Mutex;
use heapless::{String, Vec, consts::*}; use heapless::{String, Vec, consts::*};
use smoltcp as net; use smoltcp as net;
@ -37,7 +35,7 @@ fn init_log() {}
#[cfg(feature = "semihosting")] #[cfg(feature = "semihosting")]
fn init_log() { fn init_log() {
use log::LevelFilter; use log::LevelFilter;
use cortex_m_log::log::{Logger, init}; use cortex_m_log::log::{Logger, init as init_log};
use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout}; use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout};
static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None; static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
let logger = Logger { let logger = Logger {
@ -48,7 +46,7 @@ fn init_log() {
LOGGER.get_or_insert(logger) LOGGER.get_or_insert(logger)
}; };
init(logger).unwrap(); init_log(logger).unwrap();
} }
// Pull in build information (from `built` crate) // Pull in build information (from `built` crate)
@ -492,8 +490,7 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
dma1.st[1].cr.modify(|_, w| w.en().set_bit()); dma1.st[1].cr.modify(|_, w| w.en().set_bit());
} }
type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; const SCALE: f32 = ((1 << 15) - 1) as f32;
static SPIP: Mutex<RefCell<SpiPs>> = Mutex::new(RefCell::new(None));
#[link_section = ".sram1.datspi"] #[link_section = ".sram1.datspi"]
static mut DAT: u32 = 0x201; // EN | CSTART static mut DAT: u32 = 0x201; // EN | CSTART
@ -518,11 +515,26 @@ macro_rules! create_socket {
) )
} }
#[rtfm::app(device = stm32h7::stm32h7x3)]
const APP: () = {
static SPI: (stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5) = ();
#[entry] static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2];
fn main() -> ! { static mut IIR_CH: [IIR; 2] = [
let mut cp = CorePeripherals::take().unwrap(); IIR {
let dp = Peripherals::take().unwrap(); ba: [0., 0., 0., 0., 0.],
y_offset: 0.,
y_min: -SCALE - 1.,
y_max: SCALE
};
2];
// static IFACE: net::iface::EthernetInterface<'static, 'static, 'static, eth::Device> = ();
// static SOCKETS: net::socket::SocketSet<'static, 'static, 'static> = ();
#[init]
fn init(c: init::Context) -> init::LateResources {
let dp = c.device;
let cp = c.core;
let rcc = dp.RCC; let rcc = dp.RCC;
rcc_reset(&rcc); rcc_reset(&rcc);
@ -538,16 +550,18 @@ fn main() -> ! {
io_compensation_setup(&dp.SYSCFG); io_compensation_setup(&dp.SYSCFG);
// 100 MHz // 100 MHz
/*
cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core); cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core);
cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10); cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10);
cp.SYST.enable_counter(); cp.SYST.enable_counter();
cp.SYST.enable_interrupt(); cp.SYST.enable_interrupt();
unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority
*/
cp.SCB.enable_icache(); cp.SCB.enable_icache();
// TODO: ETH DMA coherence issues // TODO: ETH DMA coherence issues
// cp.SCB.enable_dcache(&mut cp.CPUID); // cp.SCB.enable_dcache(&mut cp.CPUID);
cp.DWT.enable_cycle_counter(); // cp.DWT.enable_cycle_counter();
rcc.ahb4enr.modify(|_, w| rcc.ahb4enr.modify(|_, w|
w.gpioaen().set_bit() w.gpioaen().set_bit()
@ -622,17 +636,79 @@ fn main() -> ! {
create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1);
unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); } unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); }
unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio
cp.NVIC.enable(stm32::Interrupt::ETH);
tim2_setup(&dp.TIM2); tim2_setup(&dp.TIM2);
unsafe { cp.NVIC.set_priority(stm32::Interrupt::SPI1, 0); } // highest prio init::LateResources {
cortex_m::interrupt::free(|cs| { SPI: (spi1, spi2, spi4, spi5),
cp.NVIC.enable(stm32::Interrupt::SPI1); // IFACE: iface,
SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5))); // SOCKETS: sockets,
}); }
}
#[idle]
fn idle(_: idle::Context) -> ! {
loop {
cortex_m::asm::wfi();
}
}
// seems to slow it down
// #[link_section = ".data.spi1"]
#[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 1)]
fn SPI1(c: SPI1::Context) {
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
let (spi1, spi2, spi4, spi5) = c.resources.SPI;
let iir_ch = c.resources.IIR_CH;
let iir_state = c.resources.IIR_STATE;
let sr = spi1.sr.read();
if sr.eot().bit_is_set() {
spi1.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi1.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { iir_ch[0].update(&mut iir_state[0], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi2.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
let sr = spi5.sr.read();
if sr.eot().bit_is_set() {
spi5.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi5.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { iir_ch[1].update(&mut iir_state[1], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi4.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
}
#[interrupt(resources = [], priority = 7)]
fn ETH(_: ETH::Context) {
let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA };
ETHERNET_PENDING.store(true, Ordering::Relaxed);
unsafe { eth::interrupt_handler(dma) }
}
extern "C" {
fn DCMI();
fn JPEG();
fn SDMMC();
}
};
/*
let mut last = 0; let mut last = 0;
let mut server = Server::new(); let mut server = Server::new();
loop { loop {
@ -664,7 +740,6 @@ fn main() -> ! {
cortex_m::asm::wfi(); cortex_m::asm::wfi();
} }
} }
}
#[derive(Deserialize,Serialize)] #[derive(Deserialize,Serialize)]
struct Request { struct Request {
@ -760,65 +835,11 @@ struct Status {
y1: f32 y1: f32
} }
const SCALE: f32 = ((1 << 15) - 1) as f32;
static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2];
static mut IIR_CH: [IIR; 2] = [
IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0.,
y_min: -SCALE - 1., y_max: SCALE }; 2];
// seems to slow it down
// #[link_section = ".data.spi1"]
#[interrupt]
fn SPI1() {
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
cortex_m::interrupt::free(|cs| {
let spip = SPIP.borrow(cs).borrow();
let (spi1, spi2, spi4, spi5) = spip.as_ref().unwrap();
let sr = spi1.sr.read();
if sr.eot().bit_is_set() {
spi1.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi1.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi2.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
let sr = spi5.sr.read();
if sr.eot().bit_is_set() {
spi5.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi5.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi4.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
});
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
}
#[interrupt]
fn ETH() {
let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA };
ETHERNET_PENDING.store(true, Ordering::Relaxed);
unsafe { eth::interrupt_handler(dma) }
}
#[exception] #[exception]
fn SysTick() { fn SysTick() {
TIME.fetch_add(1, Ordering::Relaxed); TIME.fetch_add(1, Ordering::Relaxed);
} }
*/
#[exception] #[exception]
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {