Removing ethernet module
This commit is contained in:
parent
86c4c1ea5e
commit
547fe1bd40
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@ -1,605 +0,0 @@
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use core::{cmp, slice};
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use smoltcp::phy;
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use smoltcp::time::Instant;
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use smoltcp::wire::EthernetAddress;
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use smoltcp::Result;
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use super::{pac};
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#[allow(dead_code)]
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mod phy_consts {
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pub const PHY_REG_BCR: u8 = 0x00;
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pub const PHY_REG_BSR: u8 = 0x01;
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pub const PHY_REG_ID1: u8 = 0x02;
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pub const PHY_REG_ID2: u8 = 0x03;
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pub const PHY_REG_ANTX: u8 = 0x04;
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pub const PHY_REG_ANRX: u8 = 0x05;
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pub const PHY_REG_ANEXP: u8 = 0x06;
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pub const PHY_REG_ANNPTX: u8 = 0x07;
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pub const PHY_REG_ANNPRX: u8 = 0x08;
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pub const PHY_REG_SSR: u8 = 0x1F; // Special Status Register
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pub const PHY_REG_CTL: u8 = 0x0D; // Ethernet PHY Register Control
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pub const PHY_REG_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data
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pub const PHY_REG_WUCSR: u16 = 0x8010;
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pub const PHY_REG_BCR_COLTEST: u16 = 1 << 7;
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pub const PHY_REG_BCR_FD: u16 = 1 << 8;
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pub const PHY_REG_BCR_ANRST: u16 = 1 << 9;
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pub const PHY_REG_BCR_ISOLATE: u16 = 1 << 10;
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pub const PHY_REG_BCR_POWERDN: u16 = 1 << 11;
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pub const PHY_REG_BCR_AN: u16 = 1 << 12;
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pub const PHY_REG_BCR_100M: u16 = 1 << 13;
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pub const PHY_REG_BCR_LOOPBACK: u16 = 1 << 14;
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pub const PHY_REG_BCR_RESET: u16 = 1 << 15;
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pub const PHY_REG_BSR_JABBER: u16 = 1 << 1;
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pub const PHY_REG_BSR_UP: u16 = 1 << 2;
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pub const PHY_REG_BSR_FAULT: u16 = 1 << 4;
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pub const PHY_REG_BSR_ANDONE: u16 = 1 << 5;
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pub const PHY_REG_SSR_ANDONE: u16 = 1 << 12;
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pub const PHY_REG_SSR_SPEED: u16 = 0b111 << 2;
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pub const PHY_REG_SSR_10BASE_HD: u16 = 0b001 << 2;
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pub const PHY_REG_SSR_10BASE_FD: u16 = 0b101 << 2;
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pub const PHY_REG_SSR_100BASE_HD: u16 = 0b010 << 2;
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pub const PHY_REG_SSR_100BASE_FD: u16 = 0b110 << 2;
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}
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use self::phy_consts::*;
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const EMAC_DES3_OWN: u32 = 0x8000_0000;
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const EMAC_DES3_CTXT: u32 = 0x4000_0000;
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const EMAC_DES3_FD: u32 = 0x2000_0000;
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const EMAC_DES3_LD: u32 = 0x1000_0000;
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const EMAC_DES3_ES: u32 = 0x0000_8000;
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const EMAC_TDES2_IOC: u32 = 0x8000_0000;
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const EMAC_RDES3_IOC: u32 = 0x4000_0000;
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const EMAC_RDES3_PL: u32 = 0x0000_7FFF;
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const EMAC_RDES3_BUF1V: u32 = 0x0100_0000;
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const EMAC_TDES2_B1L: u32 = 0x0000_3FFF;
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const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF;
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// 6 DMAC, 6 SMAC, 4 q tag, 2 ethernet type II, 1500 ip MTU, 4 CRC, 2 padding
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const ETH_BUFFER_SIZE: usize = 1524;
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const ETH_DESC_U32_SIZE: usize = 4;
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const ETH_TX_BUFFER_COUNT: usize = 4;
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const ETH_RX_BUFFER_COUNT: usize = 4;
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#[allow(dead_code)]
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mod cr_consts {
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/* For HCLK 60-100 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0;
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/* For HCLK 100-150 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1;
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/* For HCLK 20-35 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2;
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/* For HCLK 35-60 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3;
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/* For HCLK 150-250 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4;
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/* For HCLK 250-300 MHz */
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pub const ETH_MACMIIAR_CR_HCLK_DIV_124: u8 = 5;
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}
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use self::cr_consts::*;
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// set clock range in MAC MII address register
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// 200 MHz AHB clock = eth_hclk
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const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
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const PHY_ADDR: u8 = 0;
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fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 {
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while mac.macmdioar.read().mb().bit_is_set() {}
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mac.macmdioar.modify(|_, w| unsafe {
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w.pa()
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.bits(PHY_ADDR)
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.rda()
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.bits(reg_addr)
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.goc()
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.bits(0b11) // read
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.cr()
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.bits(CLOCK_RANGE)
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.mb()
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.set_bit()
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});
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while mac.macmdioar.read().mb().bit_is_set() {}
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mac.macmdiodr.read().md().bits()
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}
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fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) {
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while mac.macmdioar.read().mb().bit_is_set() {}
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mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) });
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mac.macmdioar.modify(|_, w| unsafe {
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w.pa()
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.bits(PHY_ADDR)
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.rda()
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.bits(reg_addr)
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.goc()
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.bits(0b01) // write
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.cr()
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.bits(CLOCK_RANGE)
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.mb()
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.set_bit()
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});
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while mac.macmdioar.read().mb().bit_is_set() {}
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}
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// Writes a value to an extended PHY register in MMD address space
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fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) {
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phy_write(PHY_REG_CTL, 0x0003, mac); // set address
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phy_write(PHY_REG_ADDAR, reg_addr, mac);
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phy_write(PHY_REG_CTL, 0x4003, mac); // set data
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phy_write(PHY_REG_ADDAR, reg_data, mac);
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}
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#[repr(align(4))]
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struct RxRing {
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desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT],
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pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT],
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cur_desc: usize,
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}
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impl RxRing {
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const fn new() -> Self {
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Self {
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desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_RX_BUFFER_COUNT],
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pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_RX_BUFFER_COUNT],
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cur_desc: 0,
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}
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}
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unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
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assert_eq!(self.desc_buf[0].len() % 4, 0);
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assert_eq!(self.pkt_buf[0].len() % 4, 0);
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for i in 0..self.desc_buf.len() {
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for j in 0..self.desc_buf[0].len() {
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self.desc_buf[i][j] = 0;
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}
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for j in 0..self.pkt_buf[0].len() {
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self.pkt_buf[i][j] = 0;
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}
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}
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let addr = &self.desc_buf as *const _ as u32;
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assert_eq!(addr & 0x3, 0);
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dma.dmacrx_dlar.write(|w| w.bits(addr));
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dma.dmacrx_rlr
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.write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1));
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self.cur_desc = 0;
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for _ in 0..self.desc_buf.len() {
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self.buf_release()
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}
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}
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fn next_desc(&self) -> usize {
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(self.cur_desc + 1) % self.desc_buf.len()
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}
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// not owned by DMA
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0
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}
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fn buf_valid(&self) -> bool {
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self.desc_buf[self.cur_desc][3]
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& (EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_ES | EMAC_DES3_CTXT)
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== (EMAC_DES3_FD | EMAC_DES3_LD)
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}
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unsafe fn buf_as_slice_mut<'a>(&self) -> &'a mut [u8] {
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let len = (self.desc_buf[self.cur_desc][3] & EMAC_RDES3_PL) as usize;
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let len = cmp::min(len, ETH_BUFFER_SIZE);
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let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8;
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slice::from_raw_parts_mut(addr, len)
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}
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fn buf_release(&mut self) {
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let addr = &self.pkt_buf[self.cur_desc] as *const _;
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self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
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self.desc_buf[self.cur_desc][3] =
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EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN;
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let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
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assert_eq!(addr & 0x3, 0);
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let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
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// Ensure changes to the descriptor (in particular, the OWN flag) are
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// committed before DMA engine sees tail pointer store.
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cortex_m::asm::dsb();
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dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) });
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self.cur_desc = self.next_desc();
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}
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}
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#[repr(align(4))]
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struct TxRing {
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desc_buf: [[u32; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT],
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pkt_buf: [[u8; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT],
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cur_desc: usize,
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}
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impl TxRing {
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const fn new() -> Self {
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Self {
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desc_buf: [[0; ETH_DESC_U32_SIZE]; ETH_TX_BUFFER_COUNT],
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pkt_buf: [[0; ETH_BUFFER_SIZE]; ETH_TX_BUFFER_COUNT],
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cur_desc: 0,
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}
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}
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unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
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assert_eq!(self.desc_buf[0].len() % 4, 0);
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assert_eq!(self.pkt_buf[0].len() % 4, 0);
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for i in 0..self.desc_buf.len() {
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for j in 0..self.desc_buf[0].len() {
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self.desc_buf[i][j] = 0;
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}
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for j in 0..self.pkt_buf[0].len() {
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self.pkt_buf[i][j] = 0;
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}
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}
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self.cur_desc = 0;
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let addr = &self.desc_buf as *const _ as u32;
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assert_eq!(addr & 0x3, 0);
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dma.dmactx_dlar.write(|w| w.bits(addr));
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dma.dmactx_rlr
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.write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1));
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let addr = &self.desc_buf[0] as *const _ as u32;
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assert_eq!(addr & 0x3, 0);
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dma.dmactx_dtpr.write(|w| w.bits(addr));
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}
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fn next_desc(&self) -> usize {
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(self.cur_desc + 1) % self.desc_buf.len()
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}
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// not owned by DMA
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc][3] & EMAC_DES3_OWN == 0
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}
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unsafe fn buf_as_slice_mut<'a>(&mut self, len: usize) -> &'a mut [u8] {
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let len = cmp::min(len, ETH_BUFFER_SIZE);
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self.desc_buf[self.cur_desc][2] =
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EMAC_TDES2_IOC | (len as u32 & EMAC_TDES2_B1L);
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let addr = &self.pkt_buf[self.cur_desc] as *const _ as *mut u8;
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self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
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slice::from_raw_parts_mut(addr, len)
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}
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fn buf_release(&mut self) {
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self.desc_buf[self.cur_desc][3] =
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EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD;
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self.cur_desc = self.next_desc();
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let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
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assert_eq!(addr & 0x3, 0);
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let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
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// Ensure packet contents as well as changes to the descriptor have been
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// committed before DMA engine sees the tail pointer store.
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cortex_m::asm::dsb();
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dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) });
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}
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}
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pub struct Device {
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rx: RxRing,
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tx: TxRing,
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}
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impl Device {
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pub const fn new() -> Self {
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Self {
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rx: RxRing::new(),
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tx: TxRing::new(),
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}
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}
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// Initialize the ethernet peripherals
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//
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// # Safety
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//
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// This iis transitively unsafe since it sets potentially
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// unsafe register values. Might ultimately be safe if the values
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// are correct.
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//
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// After `init` is called, `Device` shall not be moved.
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pub unsafe fn init(
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&mut self,
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mac: EthernetAddress,
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eth_mac: &pac::ETHERNET_MAC,
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eth_dma: &pac::ETHERNET_DMA,
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eth_mtl: &pac::ETHERNET_MTL,
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) {
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eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
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while eth_dma.dmamr.read().swr().bit_is_set() {}
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// 200 MHz
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eth_mac
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.mac1ustcr
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.modify(|_, w| w.tic_1us_cntr().bits(200 - 1));
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// Configuration Register
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eth_mac.maccr.modify(|_, w| {
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w.arpen()
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.clear_bit()
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.ipc()
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.set_bit()
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.ipg()
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.bits(0b000) // 96 bit
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.ecrsfd()
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.clear_bit()
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.dcrs()
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.clear_bit()
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.bl()
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.bits(0b00) // 19
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.prelen()
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.bits(0b00) // 7
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// CRC stripping for Type frames
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.cst()
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.set_bit()
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// Fast Ethernet speed
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.fes()
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.set_bit()
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// Duplex mode
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.dm()
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.set_bit()
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// Automatic pad/CRC stripping
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.acs()
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.set_bit()
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// Retry disable in half-duplex mode
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.dr()
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.set_bit()
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});
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eth_mac.macecr.modify(|_, w| {
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w.eipgen()
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.clear_bit()
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.usp()
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.clear_bit()
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.spen()
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.clear_bit()
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.dcrcc()
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.clear_bit()
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});
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// Set the MAC address
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eth_mac.maca0lr.write(|w| {
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w.addrlo().bits(
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u32::from(mac.0[0])
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| (u32::from(mac.0[1]) << 8)
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| (u32::from(mac.0[2]) << 16)
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| (u32::from(mac.0[3]) << 24),
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)
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});
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eth_mac.maca0hr.write(|w| {
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w.addrhi()
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.bits(u16::from(mac.0[4]) | (u16::from(mac.0[5]) << 8))
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});
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// frame filter register
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eth_mac.macpfr.modify(|_, w| {
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w.dntu()
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.clear_bit()
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.ipfe()
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.clear_bit()
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.vtfe()
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.clear_bit()
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.hpf()
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.clear_bit()
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.saf()
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.clear_bit()
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.saif()
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.clear_bit()
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.pcf()
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.bits(0b00)
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.dbf()
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.clear_bit()
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.pm()
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.clear_bit()
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.daif()
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.clear_bit()
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.hmc()
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.clear_bit()
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.huc()
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.clear_bit()
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// Receive All
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.ra()
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.clear_bit()
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// Promiscuous mode
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.pr()
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.clear_bit()
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});
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eth_mac.macwtr.write(|w| w.pwe().clear_bit());
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// Flow Control Register
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eth_mac.macqtx_fcr.modify(|_, w| {
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// Pause time
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w.pt().bits(0x100)
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});
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eth_mac.macrx_fcr.modify(|_, w| w);
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eth_mtl.mtlrx_qomr.modify(|_, w| {
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w
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// Receive store and forward
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.rsf()
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.set_bit()
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// Dropping of TCP/IP checksum error frames disable
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.dis_tcp_ef()
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.clear_bit()
|
||||
// Forward error frames
|
||||
.fep()
|
||||
.clear_bit()
|
||||
// Forward undersized good packets
|
||||
.fup()
|
||||
.clear_bit()
|
||||
});
|
||||
eth_mtl.mtltx_qomr.modify(|_, w| {
|
||||
w
|
||||
// Transmit store and forward
|
||||
.tsf()
|
||||
.set_bit()
|
||||
});
|
||||
|
||||
if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007)
|
||||
| (phy_read(PHY_REG_ID2, eth_mac) != 0xC131)
|
||||
{
|
||||
error!("PHY ID error!");
|
||||
}
|
||||
|
||||
phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac);
|
||||
while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET
|
||||
== PHY_REG_BCR_RESET
|
||||
{}
|
||||
phy_write_ext(PHY_REG_WUCSR, 0, eth_mac);
|
||||
phy_write(
|
||||
PHY_REG_BCR,
|
||||
PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
|
||||
eth_mac,
|
||||
);
|
||||
/*
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {};
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {};
|
||||
while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED)
|
||||
!= PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {};
|
||||
*/
|
||||
|
||||
// operation mode register
|
||||
eth_dma.dmamr.modify(|_, w| {
|
||||
w.intm()
|
||||
.bits(0b00)
|
||||
// Rx Tx priority ratio 1:1
|
||||
.pr()
|
||||
.bits(0b000)
|
||||
.txpr()
|
||||
.clear_bit()
|
||||
.da()
|
||||
.clear_bit()
|
||||
});
|
||||
// bus mode register
|
||||
eth_dma.dmasbmr.modify(|_, w| {
|
||||
// Address-aligned beats
|
||||
w.aal()
|
||||
.set_bit()
|
||||
// Fixed burst
|
||||
.fb()
|
||||
.set_bit()
|
||||
});
|
||||
eth_dma
|
||||
.dmaccr
|
||||
.modify(|_, w| w.dsl().bits(0).pblx8().clear_bit().mss().bits(536));
|
||||
eth_dma.dmactx_cr.modify(|_, w| {
|
||||
w
|
||||
// Tx DMA PBL
|
||||
.txpbl()
|
||||
.bits(32)
|
||||
.tse()
|
||||
.clear_bit()
|
||||
// Operate on second frame
|
||||
.osf()
|
||||
.clear_bit()
|
||||
});
|
||||
|
||||
eth_dma.dmacrx_cr.modify(|_, w| {
|
||||
w
|
||||
// receive buffer size
|
||||
.rbsz()
|
||||
.bits(ETH_BUFFER_SIZE as u16)
|
||||
// Rx DMA PBL
|
||||
.rxpbl()
|
||||
.bits(32)
|
||||
// Disable flushing of received frames
|
||||
.rpf()
|
||||
.clear_bit()
|
||||
});
|
||||
|
||||
self.rx.init(eth_dma);
|
||||
self.tx.init(eth_dma);
|
||||
|
||||
// Manage MAC transmission and reception
|
||||
eth_mac.maccr.modify(|_, w| {
|
||||
w.re()
|
||||
.bit(true) // Receiver Enable
|
||||
.te()
|
||||
.bit(true) // Transmiter Enable
|
||||
});
|
||||
eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
|
||||
|
||||
// Ensure ring buffer descriptors have been set up in memory before
|
||||
// enabling DMA engine.
|
||||
cortex_m::asm::dsb();
|
||||
|
||||
// Manage DMA transmission and reception
|
||||
eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
|
||||
eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit());
|
||||
|
||||
eth_dma
|
||||
.dmacsr
|
||||
.modify(|_, w| w.tps().set_bit().rps().set_bit());
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, 'b> phy::Device<'a> for &'b mut Device {
|
||||
type RxToken = RxToken<'a>;
|
||||
type TxToken = TxToken<'a>;
|
||||
|
||||
fn capabilities(&self) -> phy::DeviceCapabilities {
|
||||
let mut capabilities = phy::DeviceCapabilities::default();
|
||||
// ethernet frame type II (6 smac, 6 dmac, 2 ethertype),
|
||||
// sans CRC (4), 1500 IP MTU
|
||||
capabilities.max_transmission_unit = 1514;
|
||||
capabilities.max_burst_size = Some(self.tx.desc_buf.len());
|
||||
capabilities
|
||||
}
|
||||
|
||||
fn receive(&mut self) -> Option<(RxToken, TxToken)> {
|
||||
// Skip all queued packets with errors.
|
||||
while self.rx.buf_owned() && !self.rx.buf_valid() {
|
||||
self.rx.buf_release()
|
||||
}
|
||||
|
||||
if !(self.rx.buf_owned() && self.tx.buf_owned()) {
|
||||
return None;
|
||||
}
|
||||
|
||||
Some((RxToken(&mut self.rx), TxToken(&mut self.tx)))
|
||||
}
|
||||
|
||||
fn transmit(&mut self) -> Option<TxToken> {
|
||||
if !self.tx.buf_owned() {
|
||||
return None;
|
||||
}
|
||||
|
||||
Some(TxToken(&mut self.tx))
|
||||
}
|
||||
}
|
||||
|
||||
pub struct RxToken<'a>(&'a mut RxRing);
|
||||
|
||||
impl<'a> phy::RxToken for RxToken<'a> {
|
||||
fn consume<R, F>(self, _timestamp: Instant, f: F) -> Result<R>
|
||||
where
|
||||
F: FnOnce(&mut [u8]) -> Result<R>,
|
||||
{
|
||||
let result = f(unsafe { self.0.buf_as_slice_mut() });
|
||||
self.0.buf_release();
|
||||
result
|
||||
}
|
||||
}
|
||||
|
||||
pub struct TxToken<'a>(&'a mut TxRing);
|
||||
|
||||
impl<'a> phy::TxToken for TxToken<'a> {
|
||||
fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R>
|
||||
where
|
||||
F: FnOnce(&mut [u8]) -> Result<R>,
|
||||
{
|
||||
let result = f(unsafe { self.0.buf_as_slice_mut(len) });
|
||||
self.0.buf_release();
|
||||
result
|
||||
}
|
||||
}
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
#[panic_handler]
|
||||
#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
|
||||
fn panic(_info: &core::panic::PanicInfo) -> ! {
|
||||
let gpiod = unsafe { &*pac::GPIOD::ptr() };
|
||||
let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
|
||||
gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
|
||||
unsafe {
|
||||
core::intrinsics::abort();
|
||||
|
|
@ -34,7 +34,6 @@ use cortex_m;
|
|||
use stm32h7xx_hal as hal;
|
||||
use stm32h7xx_hal::{
|
||||
prelude::*,
|
||||
stm32 as pac,
|
||||
};
|
||||
|
||||
use embedded_hal::{
|
||||
|
|
@ -47,7 +46,6 @@ use smoltcp as net;
|
|||
#[link_section = ".sram3.eth"]
|
||||
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
|
||||
|
||||
mod eth;
|
||||
mod server;
|
||||
mod afe;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue