rxdr: 16 bit
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parent
263784ff13
commit
52a3f8c4b7
@ -369,6 +369,8 @@ fn main() -> ! {
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// at least one SCK between EOT and CSTART
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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let txdr = &spi2.txdr as *const _ as *mut u16;
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let rxdr = &spi1.rxdr as *const _ as *const u16;
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loop {
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loop {
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#[cfg(feature = "bkpt")]
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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cortex_m::asm::bkpt();
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@ -380,13 +382,14 @@ fn main() -> ! {
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if spi1.sr.read().rxp().bit_is_clear() {
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if spi1.sr.read().rxp().bit_is_clear() {
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continue;
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continue;
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}
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}
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let a = spi1.rxdr.read().rxdr().bits() as i16;
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// let a = spi1.rxdr.read().rxdr().bits() as i16;
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let a = unsafe { ptr::read_volatile(rxdr) };
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let d = (a as u16) ^ 0x8000;
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let d = (a as u16) ^ 0x8000;
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if spi2.sr.read().txp().bit_is_clear() {
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if spi2.sr.read().txp().bit_is_clear() {
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continue;
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continue;
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}
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}
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let txdr = &spi2.txdr as *const _ as *mut u16;
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// needs to be a half word write
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unsafe { ptr::write_volatile(txdr, d) };
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unsafe { ptr::write_volatile(txdr, d) };
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while spi2.sr.read().txc().bit_is_clear() {}
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while spi2.sr.read().txc().bit_is_clear() {}
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