lockin-internal: rename, adapt
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6e1444f070
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@ -74,8 +74,8 @@ const APP: () = {
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// DAC0 always generates a fixed sinusoidal output.
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// DAC0 always generates a fixed sinusoidal output.
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for (i, value) in DAC_SEQUENCE.iter().enumerate() {
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for (i, value) in DAC_SEQUENCE.iter().enumerate() {
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// Full-scale gives a +/- 12V amplitude waveform. Scale it down to give +/- 100mV.
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// Full-scale gives a +/- 10V amplitude waveform. Scale it down to give +/- 1V.
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let y = value * i16::MAX as f32 / 120.0;
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let y = value * (0.1 * i16::MAX as f32);
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// Note(unsafe): The DAC_SEQUENCE values are guaranteed to be normalized.
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// Note(unsafe): The DAC_SEQUENCE values are guaranteed to be normalized.
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let y = unsafe { y.to_int_unchecked::<i16>() };
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let y = unsafe { y.to_int_unchecked::<i16>() };
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@ -84,7 +84,8 @@ const APP: () = {
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}
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}
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let pll_phase = 0;
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let pll_phase = 0;
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let pll_frequency = 1i32 << (32 - 3); // 1/8 of the sample rate
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// 1/8 of the sample rate: log2(DAC_SEQUENCE.len()) == 3
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let pll_frequency = 1i32 << (32 - 3);
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// Harmonic index of the LO: -1 to _de_modulate the fundamental
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// Harmonic index of the LO: -1 to _de_modulate the fundamental
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let harmonic: i32 = -1;
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let harmonic: i32 = -1;
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@ -92,28 +93,23 @@ const APP: () = {
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// Demodulation LO phase offset
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// Demodulation LO phase offset
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let phase_offset: i32 = (0.7495 * i32::MAX as f32) as i32;
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let phase_offset: i32 = (0.7495 * i32::MAX as f32) as i32;
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let sample_frequency = (pll_frequency as i32).wrapping_mul(harmonic);
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let sample_frequency = (pll_frequency as i32).wrapping_mul(harmonic);
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let mut sample_phase = phase_offset
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let sample_phase = phase_offset
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.wrapping_add((pll_phase as i32).wrapping_mul(harmonic));
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.wrapping_add((pll_phase as i32).wrapping_mul(harmonic));
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let mut phase = 0i16;
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if let Some(output) = c.resources.lockin.feed(
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adc_samples.iter().map(|&i|
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// Convert to signed, MSB align the ADC sample.
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(i as i16 as i32) << 16),
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sample_phase,
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sample_frequency,
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) {
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// Convert from IQ to power and phase.
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let _power = output.abs_sqr();
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let phase = output.arg() >> 16;
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for sample in adc_samples.iter() {
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for value in dac_samples[1].iter_mut() {
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// Convert to signed, MSB align the ADC sample.
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*value = phase as u16 ^ 0x8000;
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let input = (*sample as i16 as i32) << 16;
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}
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// Obtain demodulated, filtered IQ sample.
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let output = c.resources.lockin.update(input, sample_phase);
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// Advance the sample phase.
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sample_phase = sample_phase.wrapping_add(sample_frequency);
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// Convert from IQ to phase. Scale the phase so that it fits in the DAC range. We do
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// this by shifting it down into the 16-bit range.
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phase = (output.phase() >> 16) as i16;
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}
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for value in dac_samples[1].iter_mut() {
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*value = phase as u16 ^ 0x8000
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}
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}
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}
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}
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