no midi
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parent
d3d2d4e4f8
commit
263784ff13
10
src/main.rs
10
src/main.rs
@ -260,8 +260,8 @@ fn main() -> ! {
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.moder3().output()
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.moder3().output()
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);
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);
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gpiog.odr.modify(|_, w|
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gpiog.odr.modify(|_, w|
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w.odr2().clear_bit()
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w.odr2().set_bit()
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.odr3().clear_bit()
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.odr3().set_bit()
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);
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);
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// SCK: PG11
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// SCK: PG11
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@ -298,7 +298,7 @@ fn main() -> ! {
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.sp().bits(0) // motorola
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.comm().bits(0b10) // simplex receiver
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.ioswp().clear_bit()
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.ioswp().clear_bit()
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.midi().bits(2) // master inter data idle
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.midi().bits(0) // master inter data idle
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.mssi().bits(11) // master SS idle
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.mssi().bits(11) // master SS idle
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});
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});
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spi1.cr2.modify(|_, w| unsafe {
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spi1.cr2.modify(|_, w| unsafe {
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@ -359,13 +359,14 @@ fn main() -> ! {
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.sp().bits(0) // motorola
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.sp().bits(0) // motorola
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.comm().bits(0b01) // simplex transmitter
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.comm().bits(0b01) // simplex transmitter
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.ioswp().clear_bit()
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.ioswp().clear_bit()
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.midi().bits(1) // master inter data idle
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.midi().bits(0) // master inter data idle
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.mssi().bits(0) // master SS idle
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.mssi().bits(0) // master SS idle
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});
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});
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spi2.cr2.modify(|_, w| unsafe {
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spi2.cr2.modify(|_, w| unsafe {
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w.tsize().bits(0)
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w.tsize().bits(0)
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});
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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spi2.cr1.write(|w| w.spe().set_bit());
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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loop {
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loop {
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@ -387,7 +388,6 @@ fn main() -> ! {
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}
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}
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let txdr = &spi2.txdr as *const _ as *mut u16;
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let txdr = &spi2.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr, d) };
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unsafe { ptr::write_volatile(txdr, d) };
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// at least one SCK between EOT and CSTART
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while spi2.sr.read().txc().bit_is_clear() {}
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while spi2.sr.read().txc().bit_is_clear() {}
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#[cfg(feature = "bkpt")]
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#[cfg(feature = "bkpt")]
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