Fixing CI
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@ -32,8 +32,10 @@ pub const DDS_REF_CLK: MegaHertz = MegaHertz(100);
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pub const DDS_MULTIPLIER: u8 = 5;
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pub const DDS_MULTIPLIER: u8 = 5;
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/// The DDS system clock frequency after the internal PLL multiplication.
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/// The DDS system clock frequency after the internal PLL multiplication.
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#[allow(dead_code)]
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pub const DDS_SYSTEM_CLK: MegaHertz =
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pub const DDS_SYSTEM_CLK: MegaHertz =
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MegaHertz(DDS_REF_CLK.0 * DDS_MULTIPLIER as u32);
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MegaHertz(DDS_REF_CLK.0 * DDS_MULTIPLIER as u32);
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/// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk).
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/// The divider from the DDS system clock to the SYNC_CLK output (sync-clk is always 1/4 of sysclk).
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#[allow(dead_code)]
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pub const DDS_SYNC_CLK_DIV: u8 = 4;
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pub const DDS_SYNC_CLK_DIV: u8 = 4;
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@ -30,6 +30,7 @@ extern crate panic_halt;
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#[macro_use]
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#[macro_use]
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extern crate log;
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extern crate log;
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#[allow(unused_imports)]
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use core::convert::TryInto;
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use core::convert::TryInto;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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