load process into itcm

needs newer fixed cortex-m-rt 0.6.13+unreleased
relevant? https://reviews.llvm.org/D81986

.cargo/config

@@ -1,6 +1,7 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 runner = "gdb-multiarch -q -x openocd.gdb"
 rustflags = [
+    "-C", "link-arg=--nmagic",
     "-C", "link-arg=-Tlink.x",
 # The target (below) defaults to cortex-m4
 # There currently are two different options to go beyond that:

Cargo.lock

@@ -100,6 +100,12 @@ dependencies = [
  "rustc_version",
 ]
 
+[[package]]
+name = "cc"
+version = "1.0.67"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e3c69b077ad434294d3ce9f1f6143a2a4b89a8a2d54ef813d85003a4fd1137fd"
+
 [[package]]
 name = "cfg-if"
 version = "1.0.0"
@@ -145,18 +151,13 @@ dependencies = [
 [[package]]
 name = "cortex-m-rt"
 version = "0.6.13"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "980c9d0233a909f355ed297ef122f257942de5e0a2cb1c39f60684b65bcb90fb"
 dependencies = [
  "cortex-m-rt-macros",
- "r0",
 ]
 
 [[package]]
 name = "cortex-m-rt-macros"
-version = "0.1.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4717562afbba06e760d34451919f5c3bf3ac15c7bb897e8b04862a7428378647"
+version = "0.6.11"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -572,12 +573,6 @@ dependencies = [
  "proc-macro2",
 ]
 
-[[package]]
-name = "r0"
-version = "0.2.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
-
 [[package]]
 name = "rand"
 version = "0.8.3"
@@ -720,6 +715,7 @@ version = "0.4.1"
 dependencies = [
  "ad9959",
  "asm-delay",
+ "cc",
  "cortex-m 0.6.7",
  "cortex-m-log",
  "cortex-m-rt",

Cargo.toml

@@ -47,6 +47,23 @@ smoltcp-nal = "0.1.0"
 miniconf = "0.1"
 generic-array = "0.14"
 
+[dependencies.mcp23017]
+git = "https://github.com/mrd0ll4r/mcp23017.git"
+
+[dependencies.stm32h7xx-hal]
+features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
+git = "https://github.com/stm32-rs/stm32h7xx-hal"
+branch = "master"
+
+[build-dependencies]
+cc = "1.0"
+
+[patch.crates-io.cortex-m-rt]
+path = "../cortex-m-rt"
+# 0.6.13
+# git = "https://github.com/rust-embedded/cortex-m-rt.git"
+# rev = "8c90451"
+
 [patch.crates-io.miniconf]
 git = "https://github.com/quartiq/miniconf.git"
 branch = "develop"
@@ -67,14 +84,6 @@ branch = "master"
 # a new release of smoltcp is made, we can remove this patch.
 git = "https://github.com/smoltcp-rs/smoltcp.git"
 
-[dependencies.mcp23017]
-git = "https://github.com/mrd0ll4r/mcp23017.git"
-
-[dependencies.stm32h7xx-hal]
-features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
-git = "https://github.com/stm32-rs/stm32h7xx-hal"
-branch = "master"
-
 [features]
 semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
 bkpt = [ ]

build.rs

@@ -0,0 +1,9 @@
+fn main() {
+    println!("cargo:rerun-if-changed=memory.x");
+
+    cc::Build::new()
+        .file("src/startup.S")
+        .compile("startup");
+    println!("cargo:rerun-if-changed=src/startup.S");
+}
+

memory.x

@@ -13,10 +13,6 @@ MEMORY
 }
 
 SECTIONS {
-  .itcm : ALIGN(8) {
-    *(.itcm .itcm.*);
-    . = ALIGN(8);
-    } > ITCM
   .axisram (NOLOAD) : ALIGN(8) {
     *(.axisram .axisram.*);
     . = ALIGN(8);
@@ -33,4 +29,21 @@ SECTIONS {
     *(.sram3 .sram3.*);
     . = ALIGN(4);
     } > SRAM3
-} INSERT AFTER .bss;
+  .itcm : ALIGN(8) {
+    . = ALIGN(8);
+    __sitcm = .;
+    *(.itcm .itcm.*);
+    . = ALIGN(8);
+    __eitcm = .;
+  } > ITCM AT>FLASH
+  __siitcm = LOADADDR(.itcm);
+
+/* This may be the only insert location that doesn't affect those __[es]...
+ * that are (unfortunately) placed outside their sections */
+} INSERT BEFORE .uninit;
+
+ASSERT(__sitcm % 8 == 0 && __eitcm % 8 == 0, "
+BUG(cortex-m-rt): .itcm is not 8-byte aligned");
+
+ASSERT(__siitcm % 4 == 0, "
+BUG(cortex-m-rt): the LMA of .itcm is not 4-byte aligned");

src/bin/dual-iir.rs

@@ -110,6 +110,8 @@ const APP: () = {
     /// Because the ADC and DAC operate at the same rate, these two constraints actually implement
     /// the same time bounds, meeting one also means the other is also met.
     #[task(binds=DMA1_STR4, resources=[adcs, dacs, iir_state, iir_ch], priority=2)]
+    #[inline(never)]
+    #[link_section = ".itcm.process"]
     fn process(c: process::Context) {
         let adc_samples = [
             c.resources.adcs.0.acquire_buffer(),

src/hardware/mod.rs

@@ -58,11 +58,11 @@ fn panic(_info: &core::panic::PanicInfo) -> ! {
 }
 
 #[cortex_m_rt::exception]
-fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
+unsafe fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
     panic!("HardFault at {:#?}", ef);
 }
 
 #[cortex_m_rt::exception]
-fn DefaultHandler(irqn: i16) {
+unsafe fn DefaultHandler(irqn: i16) {
     panic!("Unhandled exception (IRQn = {})", irqn);
 }

src/startup.S

@@ -0,0 +1,28 @@
+.cfi_sections .debug_frame
+
+# .thumb
+.section .text.pre_init, "ax"
+.globl __pre_init
+.type __pre_init,%function
+.thumb_func
+.cfi_startproc
+__pre_init:
+  # Analogous to cortex-m-rt Reset code for .data copying.
+  # Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the
+  # linker script. Copy from r2 into r0 until r0 reaches r1.
+  ldr r0,=__sitcm
+  ldr r1,=__eitcm
+  ldr r2,=__siitcm
+1:
+  cmp r1, r0
+  beq 2f
+  # load 1 word from r2 to r3, inc r2
+  ldm r2!, {r3}
+  # store 1 word from r3 to r0, inc r0
+  stm r0!, {r3}
+  b 1b
+2:
+  dsb
+  isb
+  bx lr
+.cfi_endproc