Updating after review
parent
f4a4357396
commit
14a647867a
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@ -124,7 +124,8 @@ impl<I: Interface> Ad9959<I> {
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reset_pin.set_high().or(Err(Error::Pin))?;
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// Delay for at least 1 SYNC_CLK period for the reset to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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reset_pin.set_low().or(Err(Error::Pin))?;
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@ -143,7 +144,8 @@ impl<I: Interface> Ad9959<I> {
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io_update.set_high().or(Err(Error::Pin))?;
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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io_update.set_low().or(Err(Error::Pin))?;
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@ -157,7 +159,8 @@ impl<I: Interface> Ad9959<I> {
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// active. This is likely due to needing to wait at least 1 clock cycle of the DDS for the
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// interface update to occur.
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK). We use 5uS instead of 4uS to
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// guarantee conformance with datasheet requirements.
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delay.delay_us(5);
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// Read back the CSR to ensure it specifies the mode correctly.
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@ -552,12 +555,6 @@ impl ProfileSerializer {
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pow: Option<u16>,
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acr: Option<u16>,
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) {
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// The user should have provided something to update.
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assert!(
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(ftw.is_some() || acr.is_some() || pow.is_some())
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&& channels.len() > 0
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);
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let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8);
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for channel in channels.iter() {
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csr.set_bit(4 + *channel as usize, true);
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@ -581,8 +578,6 @@ impl ProfileSerializer {
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/// Add a register write to the serialization data.
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fn add_write(&mut self, register: Register, value: &[u8]) {
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let data = &mut self.data[self.index..];
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assert!(value.len() + 1 <= data.len());
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data[0] = register as u8;
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data[1..][..value.len()].copy_from_slice(value);
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self.index += value.len() + 1;
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@ -592,24 +587,24 @@ impl ProfileSerializer {
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///
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/// # Note
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/// The serialized profile will be padded to the next 32-bit word boundary by adding dummy
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/// writes to the CSR or FR2 registers.
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/// writes to the CSR or LSRR registers.
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///
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/// # Returns
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/// A slice of `u32` words representing the serialized profile.
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pub fn finalize<'a>(&'a mut self) -> &[u32] {
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// Pad the buffer to 32-bit alignment by adding dummy writes to CSR and FR2.
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// Pad the buffer to 32-bit alignment by adding dummy writes to CSR and LSRR.
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let padding = 4 - (self.index % 4);
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match padding {
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0 => {}
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1 => {
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// For a pad size of 1, we have to pad with 5 bytes to align things.
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self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
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self.add_write(Register::FR2, &[0, 0, 0]);
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self.add_write(Register::LSRR, &[0, 0, 0]);
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}
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2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
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3 => self.add_write(Register::FR2, &[0, 0, 0]),
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3 => self.add_write(Register::LSRR, &[0, 0, 0]),
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_ => panic!("Invalid"),
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_ => unreachable!(),
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}
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unsafe {
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core::slice::from_raw_parts::<'a, u32>(
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@ -68,28 +68,39 @@ impl HighResTimerE {
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// Determine the clock divider, which may be 1, 2, or 4. We will choose a clock divider that
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// allows us the highest resolution per tick, so lower dividers are favored.
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let divider: u8 = if source_cycles < 0xFFDF {
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let setting: u8 = if source_cycles < 0xFFDF {
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1
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} else if (source_cycles / 2) < 0xFFDF {
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2
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} else if (source_cycles / 4) < 0xFFDF {
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4
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3
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} else {
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panic!("Unattainable timing parameters!");
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};
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let divider = 1 << (setting - 1);
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// The period register must be greater than or equal to 3 cycles.
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let period = (source_cycles / divider as u32) as u16;
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assert!(period > 2);
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// We now have the prescaler and the period registers. Configure the timer.
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// Note(unsafe): The prescaler is guaranteed to be greater than or equal to 4 (minimum
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// allowed value) due to the addition. The setting is always 1, 2, or 3, which represents
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// all valid values.
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self.timer
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.timecr
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.modify(|_, w| unsafe { w.ck_pscx().bits(divider + 4) });
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.modify(|_, w| unsafe { w.ck_pscx().bits(setting + 4) });
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// Note(unsafe): The period register is guaranteed to be a 16-bit value, which will fit in
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// this register.
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self.timer.perer.write(|w| unsafe { w.perx().bits(period) });
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// Configure the comparator 1 level.
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let offset = (set_offset * source_frequency as f32) as u16;
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// Note(unsafe): The offset is always a 16-bit value, so is always valid for values >= 3, as
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// specified by the datasheet.
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assert!(offset >= 3);
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self.timer
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.cmp1er
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.write(|w| unsafe { w.cmp1x().bits(offset) });
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16
src/main.rs
16
src/main.rs
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@ -625,12 +625,16 @@ const APP: () = {
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ccdr.peripheral.HRTIM,
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);
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// IO_Update should be latched for 50ns after the QSPI profile write. Profile writes
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// are always 16 bytes, with 2 cycles required per byte, coming out to a total of 32
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// QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an
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// offset of 800nS. We use 900ns to be safe - note that the timer is triggered after
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// the QSPI write, which can take approximately 120nS, so there is additional
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// margin.
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// IO_Update should be latched for 4 SYNC_CLK cycles after the QSPI profile
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// write. With pounder SYNC_CLK running at 100MHz (1/4 of the pounder reference
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// clock of 400MHz), this corresponds to 40ns. To accomodate rounding errors, we
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// use 50ns instead.
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//
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// Profile writes are always 16 bytes, with 2 cycles required per byte, coming
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// out to a total of 32 QSPI clock cycles. The QSPI is configured for 40MHz, so
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// this comes out to an offset of 800nS. We use 900ns to be safe - note that the
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// timer is triggered after the QSPI write, which can take approximately 120nS,
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// so there is additional margin.
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hrtimer.configure_single_shot(
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hrtimer::Channel::Two,
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50_e-9,
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@ -58,6 +58,10 @@ impl DdsOutput {
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// fashion.
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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if regs.sr.read().flevel() != 0 {
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warn!("QSPI stalling")
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}
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for word in profile.iter() {
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// Note(unsafe): We are writing to the SPI TX FIFO in a raw manner for performance. This
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// is safe because we know the data register is a valid address to write to.
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