Merge pull request #228 from matthuszagh/lockin-bin

Lock-in integration testing

dsp/src/lib.rs

@@ -17,7 +17,7 @@ pub type Complex<T> = (T, T);
 /// Shifted and rounded value.
 #[inline(always)]
 pub fn shift_round(x: i32, shift: usize) -> i32 {
-    (x + (1 << (shift - 1))) >> shift
+    x.saturating_add(1 << (shift - 1)) >> shift
 }
 
 /// Integer division, round up half.

dsp/src/reciprocal_pll.rs

@@ -62,11 +62,18 @@ impl TimestampHandler {
             self.reference_frequency = frequency as u32 as i64;
         }
 
-        let demodulation_frequency = divide_round(
+        let demodulation_frequency: u32;
+        let demodulation_initial_phase: u32;
+
+        if self.reference_frequency == 0 {
+            demodulation_frequency = u32::MAX;
+            demodulation_initial_phase = u32::MAX;
+        } else {
+            demodulation_frequency = divide_round(
                 1 << (32 + self.adc_sample_ticks_log2),
                 self.reference_frequency,
             ) as u32;
-        let demodulation_initial_phase = divide_round(
+            demodulation_initial_phase = divide_round(
                 (((self.batch_index as i64)
                     << (self.adc_sample_ticks_log2
                         + self.sample_buffer_size_log2))
@@ -74,6 +81,7 @@ impl TimestampHandler {
                     << 32,
                 self.reference_frequency,
             ) as u32;
+        }
 
         if self.batch_index
             < (1 << (32

src/main.rs

@@ -1019,9 +1019,9 @@ const APP: () = {
 
                 // shift cos/sin before multiplying to avoid i64 multiplication
                 signal.0 =
-                    adc_samples[0][i] as i16 as i32 * shift_round(cos, 16);
-                signal.1 =
                     adc_samples[0][i] as i16 as i32 * shift_round(sin, 16);
+                signal.1 =
+                    adc_samples[0][i] as i16 as i32 * shift_round(cos, 16);
 
                 signal.0 =
                     iir_lockin.update(&mut iir_state_lockin[0], signal.0);