2021-01-18 23:47:47 +08:00
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///! Stabilizer hardware configuration
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///!
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///! This file contains all of the hardware-specific configuration of Stabilizer.
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use stm32h7xx_hal::{
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self as hal,
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ethernet::{self, PHY},
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prelude::*,
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};
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2021-01-31 01:48:27 +08:00
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use smoltcp_nal::smoltcp;
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2021-01-18 23:47:47 +08:00
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use super::{
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2021-02-17 19:08:03 +08:00
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adc, afe, cycle_counter::CycleCounter, dac, design_parameters,
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digital_input_stamper, eeprom, pounder, timers, DdsOutput, NetworkStack,
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AFE0, AFE1,
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2021-01-18 23:47:47 +08:00
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};
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2021-01-31 01:48:27 +08:00
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pub struct NetStorage {
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pub ip_addrs: [smoltcp::wire::IpCidr; 1],
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pub sockets: [Option<smoltcp::socket::SocketSetItem<'static>>; 1],
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pub neighbor_cache:
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[Option<(smoltcp::wire::IpAddress, smoltcp::iface::Neighbor)>; 8],
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pub routes_cache:
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[Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 8],
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pub tx_storage: [u8; 4096],
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pub rx_storage: [u8; 4096],
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}
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2021-01-18 23:47:47 +08:00
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/// The available networking devices on Stabilizer.
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pub struct NetworkDevices {
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2021-01-26 21:28:06 +08:00
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pub stack: NetworkStack,
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2021-01-18 23:47:47 +08:00
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pub phy: ethernet::phy::LAN8742A<ethernet::EthernetMAC>,
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}
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/// The available hardware interfaces on Stabilizer.
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pub struct StabilizerDevices {
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pub afes: (AFE0, AFE1),
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pub adcs: (adc::Adc0Input, adc::Adc1Input),
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pub dacs: (dac::Dac0Output, dac::Dac1Output),
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pub timestamper: digital_input_stamper::InputStamper,
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pub adc_dac_timer: timers::SamplingTimer,
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pub timestamp_timer: timers::TimestampTimer,
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pub net: NetworkDevices,
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2021-02-17 19:08:03 +08:00
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pub cycle_counter: CycleCounter,
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2021-01-18 23:47:47 +08:00
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}
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/// The available Pounder-specific hardware interfaces.
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pub struct PounderDevices {
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pub pounder: pounder::PounderDevices,
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pub dds_output: DdsOutput,
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#[cfg(feature = "pounder_v1_1")]
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pub timestamper: pounder::timestamp::Timestamper,
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}
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#[link_section = ".sram3.eth"]
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/// Static storage for the ethernet DMA descriptor ring.
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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/// Static, global-scope network storage for the ethernet interface.
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///
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/// This is a static singleton so that the network storage can be referenced from all contexts.
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [smoltcp::wire::IpCidr::Ipv6(
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smoltcp::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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2021-01-26 21:28:06 +08:00
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routes_cache: [None; 8],
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sockets: [None; 1],
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tx_storage: [0; 4096],
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rx_storage: [0; 4096],
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2021-01-18 23:47:47 +08:00
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};
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/// Configure the stabilizer hardware for operation.
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///
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/// # Args
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/// * `core` - The RTIC core for configuring the cortex-M core of the device.
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/// * `device` - The microcontroller peripherals to be configured.
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///
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/// # Returns
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/// (stabilizer, pounder) where `stabilizer` is a `StabilizerDevices` structure containing all
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/// stabilizer hardware interfaces in a disabled state. `pounder` is an `Option` containing
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/// `Some(devices)` if pounder is detected, where `devices` is a `PounderDevices` structure
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/// containing all of the pounder hardware interfaces in a disabled state.
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pub fn setup(
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mut core: rtic::export::Peripherals,
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device: stm32h7xx_hal::stm32::Peripherals,
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) -> (StabilizerDevices, Option<PounderDevices>) {
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let pwr = device.PWR.constrain();
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let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
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device.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Clear reset flags.
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device.RCC.rsr.write(|w| w.rmvf().set_bit());
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// Select the PLLs for SPI.
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device
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.RCC
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.d2ccip1r
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.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let rcc = device.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.hclk(200.mhz())
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.per_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &device.SYSCFG);
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#[cfg(feature = "semihosting")]
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{
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use cortex_m_log::log::{init as init_log, Logger};
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use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
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static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
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let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
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};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
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let mut delay = hal::delay::Delay::new(core.SYST, ccdr.clocks);
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let gpioa = device.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = device.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = device.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = device.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = device.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = device.GPIOF.split(ccdr.peripheral.GPIOF);
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let mut gpiog = device.GPIOG.split(ccdr.peripheral.GPIOG);
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let dma_streams =
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hal::dma::dma::StreamsTuple::new(device.DMA1, ccdr.peripheral.DMA1);
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|
2021-02-16 22:58:16 +08:00
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// Early, before the DMA1 peripherals (#272)
|
2021-02-16 21:12:13 +08:00
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#[cfg(feature = "pounder_v1_1")]
|
2021-02-16 22:22:58 +08:00
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let dma2_streams =
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hal::dma::dma::StreamsTuple::new(device.DMA2, ccdr.peripheral.DMA2);
|
2021-02-16 21:12:13 +08:00
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|
2021-01-18 23:47:47 +08:00
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// Configure timer 2 to trigger conversions for the ADC
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let mut sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
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// dont-care.
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let mut timer2 =
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device
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.TIM2
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.timer(1.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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// period below.
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timer2.pause();
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timer2.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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let mut sampling_timer = timers::SamplingTimer::new(timer2);
|
2021-02-04 19:48:25 +08:00
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sampling_timer
|
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.set_period_ticks((design_parameters::ADC_SAMPLE_TICKS - 1) as u32);
|
2021-01-18 23:47:47 +08:00
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// The sampling timer is used as the master timer for the shadow-sampling timer. Thus,
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// it generates a trigger whenever it is enabled.
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sampling_timer
|
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|
};
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let mut shadow_sampling_timer = {
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// The timer frequency is manually adjusted below, so the 1KHz setting here is a
|
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|
|
// dont-care.
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let mut timer3 =
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device
|
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.TIM3
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.timer(1.khz(), ccdr.peripheral.TIM3, &ccdr.clocks);
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// Configure the timer to count at the designed tick rate. We will manually set the
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|
// period below.
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timer3.pause();
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timer3.reset_counter();
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timer3.set_tick_freq(design_parameters::TIMER_FREQUENCY);
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|
|
let mut shadow_sampling_timer =
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|
|
timers::ShadowSamplingTimer::new(timer3);
|
2021-02-04 19:48:25 +08:00
|
|
|
shadow_sampling_timer
|
|
|
|
.set_period_ticks(design_parameters::ADC_SAMPLE_TICKS - 1);
|
2021-01-18 23:47:47 +08:00
|
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|
|
// The shadow sampling timer is a slave-mode timer to the sampling timer. It should
|
|
|
|
// always be in-sync - thus, we configure it to operate in slave mode using "Trigger
|
|
|
|
// mode".
|
|
|
|
// For TIM3, TIM2 can be made the internal trigger connection using ITR1. Thus, the
|
|
|
|
// SamplingTimer start now gates the start of the ShadowSamplingTimer.
|
|
|
|
shadow_sampling_timer.set_slave_mode(
|
|
|
|
timers::TriggerSource::Trigger1,
|
|
|
|
timers::SlaveMode::Trigger,
|
|
|
|
);
|
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|
|
|
|
|
|
shadow_sampling_timer
|
|
|
|
};
|
|
|
|
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|
|
let sampling_timer_channels = sampling_timer.channels();
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|
|
let shadow_sampling_timer_channels = shadow_sampling_timer.channels();
|
|
|
|
|
|
|
|
let mut timestamp_timer = {
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|
|
|
// The timer frequency is manually adjusted below, so the 1KHz setting here is a
|
|
|
|
// dont-care.
|
|
|
|
let mut timer5 =
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|
|
|
device
|
|
|
|
.TIM5
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|
|
.timer(1.khz(), ccdr.peripheral.TIM5, &ccdr.clocks);
|
|
|
|
|
|
|
|
// Configure the timer to count at the designed tick rate. We will manually set the
|
|
|
|
// period below.
|
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|
|
timer5.pause();
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|
|
timer5.set_tick_freq(design_parameters::TIMER_FREQUENCY);
|
|
|
|
|
2021-02-02 21:34:48 +08:00
|
|
|
// The timestamp timer runs at the counter cycle period as the sampling timers.
|
|
|
|
// To accomodate this, we manually set the prescaler identical to the sample
|
|
|
|
// timer, but use maximum overflow period.
|
2021-01-18 23:47:47 +08:00
|
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|
let mut timer = timers::TimestampTimer::new(timer5);
|
|
|
|
|
2021-02-02 22:46:50 +08:00
|
|
|
// TODO: Check hardware synchronization of timestamping and the sampling timers
|
|
|
|
// for phase shift determinism.
|
|
|
|
|
2021-02-02 18:36:10 +08:00
|
|
|
timer.set_period_ticks(u32::MAX);
|
2021-01-18 23:47:47 +08:00
|
|
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|
|
|
|
timer
|
|
|
|
};
|
|
|
|
|
|
|
|
let timestamp_timer_channels = timestamp_timer.channels();
|
|
|
|
|
|
|
|
// Configure the SPI interfaces to the ADCs and DACs.
|
|
|
|
let adcs = {
|
|
|
|
let adc0 = {
|
|
|
|
let spi_miso = gpiob
|
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|
|
.pb14
|
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|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_sck = gpiob
|
|
|
|
.pb10
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _spi_nss = gpiob
|
|
|
|
.pb9
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
|
|
})
|
|
|
|
.manage_cs()
|
|
|
|
.suspend_when_inactive()
|
|
|
|
.communication_mode(hal::spi::CommunicationMode::Receiver)
|
|
|
|
.cs_delay(design_parameters::ADC_SETUP_TIME);
|
|
|
|
|
|
|
|
let spi: hal::spi::Spi<_, _, u16> = device.SPI2.spi(
|
|
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
|
|
config,
|
|
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
|
|
ccdr.peripheral.SPI2,
|
|
|
|
&ccdr.clocks,
|
|
|
|
);
|
|
|
|
|
|
|
|
adc::Adc0Input::new(
|
|
|
|
spi,
|
|
|
|
dma_streams.0,
|
|
|
|
dma_streams.1,
|
|
|
|
dma_streams.2,
|
|
|
|
sampling_timer_channels.ch1,
|
|
|
|
shadow_sampling_timer_channels.ch1,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
let adc1 = {
|
|
|
|
let spi_miso = gpiob
|
|
|
|
.pb4
|
|
|
|
.into_alternate_af6()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_sck = gpioc
|
|
|
|
.pc10
|
|
|
|
.into_alternate_af6()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _spi_nss = gpioa
|
|
|
|
.pa15
|
|
|
|
.into_alternate_af6()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
|
|
})
|
|
|
|
.manage_cs()
|
|
|
|
.suspend_when_inactive()
|
|
|
|
.communication_mode(hal::spi::CommunicationMode::Receiver)
|
|
|
|
.cs_delay(design_parameters::ADC_SETUP_TIME);
|
|
|
|
|
|
|
|
let spi: hal::spi::Spi<_, _, u16> = device.SPI3.spi(
|
|
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
|
|
config,
|
|
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
|
|
ccdr.peripheral.SPI3,
|
|
|
|
&ccdr.clocks,
|
|
|
|
);
|
|
|
|
|
|
|
|
adc::Adc1Input::new(
|
|
|
|
spi,
|
|
|
|
dma_streams.3,
|
|
|
|
dma_streams.4,
|
|
|
|
dma_streams.5,
|
|
|
|
sampling_timer_channels.ch2,
|
|
|
|
shadow_sampling_timer_channels.ch2,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
(adc0, adc1)
|
|
|
|
};
|
|
|
|
|
|
|
|
let dacs = {
|
|
|
|
let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap();
|
|
|
|
let _dac0_ldac_n =
|
|
|
|
gpioe.pe11.into_push_pull_output().set_low().unwrap();
|
|
|
|
let _dac1_ldac_n =
|
|
|
|
gpioe.pe15.into_push_pull_output().set_low().unwrap();
|
|
|
|
|
|
|
|
let dac0_spi = {
|
|
|
|
let spi_miso = gpioe
|
|
|
|
.pe5
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_sck = gpioe
|
|
|
|
.pe2
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _spi_nss = gpioe
|
|
|
|
.pe4
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
|
|
})
|
|
|
|
.manage_cs()
|
|
|
|
.suspend_when_inactive()
|
|
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
|
|
.swap_mosi_miso();
|
|
|
|
|
|
|
|
device.SPI4.spi(
|
|
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
|
|
config,
|
|
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
|
|
ccdr.peripheral.SPI4,
|
|
|
|
&ccdr.clocks,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
let dac1_spi = {
|
|
|
|
let spi_miso = gpiof
|
|
|
|
.pf8
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_sck = gpiof
|
|
|
|
.pf7
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _spi_nss = gpiof
|
|
|
|
.pf6
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
|
|
})
|
|
|
|
.manage_cs()
|
|
|
|
.communication_mode(hal::spi::CommunicationMode::Transmitter)
|
|
|
|
.suspend_when_inactive()
|
|
|
|
.swap_mosi_miso();
|
|
|
|
|
|
|
|
device.SPI5.spi(
|
|
|
|
(spi_sck, spi_miso, hal::spi::NoMosi),
|
|
|
|
config,
|
|
|
|
design_parameters::ADC_DAC_SCK_MAX,
|
|
|
|
ccdr.peripheral.SPI5,
|
|
|
|
&ccdr.clocks,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
let dac0 = dac::Dac0Output::new(
|
|
|
|
dac0_spi,
|
|
|
|
dma_streams.6,
|
|
|
|
sampling_timer_channels.ch3,
|
|
|
|
);
|
|
|
|
let dac1 = dac::Dac1Output::new(
|
|
|
|
dac1_spi,
|
|
|
|
dma_streams.7,
|
|
|
|
sampling_timer_channels.ch4,
|
|
|
|
);
|
|
|
|
(dac0, dac1)
|
|
|
|
};
|
|
|
|
|
|
|
|
let afes = {
|
|
|
|
let afe0 = {
|
|
|
|
let a0_pin = gpiof.pf2.into_push_pull_output();
|
|
|
|
let a1_pin = gpiof.pf5.into_push_pull_output();
|
|
|
|
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
|
|
|
|
};
|
|
|
|
|
|
|
|
let afe1 = {
|
|
|
|
let a0_pin = gpiod.pd14.into_push_pull_output();
|
|
|
|
let a1_pin = gpiod.pd15.into_push_pull_output();
|
|
|
|
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
|
|
|
|
};
|
|
|
|
|
|
|
|
(afe0, afe1)
|
|
|
|
};
|
|
|
|
|
|
|
|
let input_stamper = {
|
|
|
|
let trigger = gpioa.pa3.into_alternate_af2();
|
|
|
|
digital_input_stamper::InputStamper::new(
|
|
|
|
trigger,
|
|
|
|
timestamp_timer_channels.ch4,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
let mut eeprom_i2c = {
|
|
|
|
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
|
|
|
|
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
|
|
|
|
device.I2C2.i2c(
|
|
|
|
(scl, sda),
|
|
|
|
100.khz(),
|
|
|
|
ccdr.peripheral.I2C2,
|
|
|
|
&ccdr.clocks,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
// Configure ethernet pins.
|
|
|
|
{
|
|
|
|
// Reset the PHY before configuring pins.
|
|
|
|
let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
|
|
|
|
eth_phy_nrst.set_low().unwrap();
|
|
|
|
delay.delay_us(200u8);
|
|
|
|
eth_phy_nrst.set_high().unwrap();
|
|
|
|
let _rmii_ref_clk = gpioa
|
|
|
|
.pa1
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_mdio = gpioa
|
|
|
|
.pa2
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_mdc = gpioc
|
|
|
|
.pc1
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_crs_dv = gpioa
|
|
|
|
.pa7
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_rxd0 = gpioc
|
|
|
|
.pc4
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_rxd1 = gpioc
|
|
|
|
.pc5
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_tx_en = gpiob
|
|
|
|
.pb11
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_txd0 = gpiob
|
|
|
|
.pb12
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let _rmii_txd1 = gpiog
|
|
|
|
.pg14
|
|
|
|
.into_alternate_af11()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
}
|
|
|
|
|
|
|
|
let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
|
|
|
|
Err(_) => {
|
|
|
|
info!("Could not read EEPROM, using default MAC address");
|
|
|
|
smoltcp::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
|
|
|
|
}
|
|
|
|
Ok(raw_mac) => smoltcp::wire::EthernetAddress(raw_mac),
|
|
|
|
};
|
|
|
|
|
|
|
|
let network_devices = {
|
|
|
|
// Configure the ethernet controller
|
|
|
|
let (eth_dma, eth_mac) = unsafe {
|
|
|
|
ethernet::new_unchecked(
|
|
|
|
device.ETHERNET_MAC,
|
|
|
|
device.ETHERNET_MTL,
|
|
|
|
device.ETHERNET_DMA,
|
|
|
|
&mut DES_RING,
|
|
|
|
mac_addr,
|
|
|
|
ccdr.peripheral.ETH1MAC,
|
|
|
|
&ccdr.clocks,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
// Reset and initialize the ethernet phy.
|
|
|
|
let mut lan8742a =
|
|
|
|
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
|
|
|
|
lan8742a.phy_reset();
|
|
|
|
lan8742a.phy_init();
|
|
|
|
|
|
|
|
unsafe { ethernet::enable_interrupt() };
|
|
|
|
|
|
|
|
let store = unsafe { &mut NET_STORE };
|
|
|
|
|
|
|
|
store.ip_addrs[0] = smoltcp::wire::IpCidr::new(
|
2021-02-02 02:32:20 +08:00
|
|
|
smoltcp::wire::IpAddress::v4(10, 34, 16, 103),
|
2021-01-18 23:47:47 +08:00
|
|
|
24,
|
|
|
|
);
|
|
|
|
|
2021-02-03 21:02:20 +08:00
|
|
|
let default_v4_gw = smoltcp::wire::Ipv4Address::new(10, 34, 16, 1);
|
2021-01-31 01:48:27 +08:00
|
|
|
let mut routes =
|
|
|
|
smoltcp::iface::Routes::new(&mut store.routes_cache[..]);
|
2021-01-18 23:47:47 +08:00
|
|
|
routes.add_default_ipv4_route(default_v4_gw).unwrap();
|
|
|
|
|
|
|
|
let neighbor_cache =
|
|
|
|
smoltcp::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
|
|
|
|
|
|
|
|
let interface = smoltcp::iface::EthernetInterfaceBuilder::new(eth_dma)
|
|
|
|
.ethernet_addr(mac_addr)
|
|
|
|
.neighbor_cache(neighbor_cache)
|
|
|
|
.ip_addrs(&mut store.ip_addrs[..])
|
|
|
|
.routes(routes)
|
|
|
|
.finalize();
|
|
|
|
|
2021-01-26 21:28:06 +08:00
|
|
|
let sockets = {
|
|
|
|
// Note(unsafe): Configuration is only called once, so we only access the global
|
|
|
|
// storage a single time.
|
2021-01-27 02:14:23 +08:00
|
|
|
let socket_storage = unsafe { &mut NET_STORE.sockets[..] };
|
2021-01-26 21:28:06 +08:00
|
|
|
let mut sockets = smoltcp::socket::SocketSet::new(socket_storage);
|
|
|
|
|
|
|
|
let tcp_socket = {
|
2021-01-27 02:14:23 +08:00
|
|
|
let rx_buffer = {
|
|
|
|
// Note(unsafe): Configuration is only called once, so we only access the global
|
|
|
|
// storage a single time.
|
|
|
|
let storage = unsafe { &mut NET_STORE.rx_storage[..] };
|
|
|
|
smoltcp::socket::TcpSocketBuffer::new(storage)
|
|
|
|
};
|
|
|
|
|
|
|
|
let tx_buffer = {
|
|
|
|
// Note(unsafe): Configuration is only called once, so we only access the global
|
|
|
|
// storage a single time.
|
|
|
|
let storage = unsafe { &mut NET_STORE.tx_storage[..] };
|
|
|
|
smoltcp::socket::TcpSocketBuffer::new(storage)
|
|
|
|
};
|
|
|
|
|
|
|
|
smoltcp::socket::TcpSocket::new(rx_buffer, tx_buffer)
|
2021-01-26 21:28:06 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
sockets.add(tcp_socket);
|
|
|
|
sockets
|
|
|
|
};
|
|
|
|
|
2021-01-18 23:47:47 +08:00
|
|
|
NetworkDevices {
|
2021-01-31 01:48:27 +08:00
|
|
|
stack: smoltcp_nal::NetworkStack::new(interface, sockets),
|
2021-01-18 23:47:47 +08:00
|
|
|
phy: lan8742a,
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
|
|
|
|
let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
|
|
|
|
let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
|
|
|
|
let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
|
|
|
|
|
|
|
|
fp_led_0.set_low().unwrap();
|
|
|
|
fp_led_1.set_low().unwrap();
|
|
|
|
fp_led_2.set_low().unwrap();
|
|
|
|
fp_led_3.set_low().unwrap();
|
|
|
|
|
|
|
|
// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
|
|
|
|
let pounder_pgood = gpiob.pb13.into_pull_down_input();
|
|
|
|
delay.delay_ms(2u8);
|
|
|
|
let pounder = if pounder_pgood.is_high().unwrap() {
|
|
|
|
let ad9959 = {
|
|
|
|
let qspi_interface = {
|
|
|
|
// Instantiate the QUADSPI pins and peripheral interface.
|
|
|
|
let qspi_pins = {
|
|
|
|
let _qspi_ncs = gpioc
|
|
|
|
.pc11
|
|
|
|
.into_alternate_af9()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let clk = gpiob
|
|
|
|
.pb2
|
|
|
|
.into_alternate_af9()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let io0 = gpioe
|
|
|
|
.pe7
|
|
|
|
.into_alternate_af10()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let io1 = gpioe
|
|
|
|
.pe8
|
|
|
|
.into_alternate_af10()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let io2 = gpioe
|
|
|
|
.pe9
|
|
|
|
.into_alternate_af10()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let io3 = gpioe
|
|
|
|
.pe10
|
|
|
|
.into_alternate_af10()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
(clk, io0, io1, io2, io3)
|
|
|
|
};
|
|
|
|
|
|
|
|
let qspi = hal::qspi::Qspi::bank2(
|
|
|
|
device.QUADSPI,
|
|
|
|
qspi_pins,
|
|
|
|
design_parameters::POUNDER_QSPI_FREQUENCY,
|
|
|
|
&ccdr.clocks,
|
|
|
|
ccdr.peripheral.QSPI,
|
|
|
|
);
|
|
|
|
|
|
|
|
pounder::QspiInterface::new(qspi).unwrap()
|
|
|
|
};
|
|
|
|
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
|
|
let reset_pin = gpiog.pg6.into_push_pull_output();
|
|
|
|
#[cfg(not(feature = "pounder_v1_1"))]
|
|
|
|
let reset_pin = gpioa.pa0.into_push_pull_output();
|
|
|
|
|
|
|
|
let mut io_update = gpiog.pg7.into_push_pull_output();
|
|
|
|
|
|
|
|
let ref_clk: hal::time::Hertz =
|
|
|
|
design_parameters::DDS_REF_CLK.into();
|
|
|
|
|
2021-02-08 22:24:52 +08:00
|
|
|
let mut ad9959 = ad9959::Ad9959::new(
|
2021-01-18 23:47:47 +08:00
|
|
|
qspi_interface,
|
|
|
|
reset_pin,
|
|
|
|
&mut io_update,
|
|
|
|
&mut delay,
|
|
|
|
ad9959::Mode::FourBitSerial,
|
|
|
|
ref_clk.0 as f32,
|
|
|
|
design_parameters::DDS_MULTIPLIER,
|
|
|
|
)
|
|
|
|
.unwrap();
|
|
|
|
|
2021-02-08 22:24:52 +08:00
|
|
|
ad9959.self_test().unwrap();
|
|
|
|
|
2021-01-18 23:47:47 +08:00
|
|
|
// Return IO_Update
|
|
|
|
gpiog.pg7 = io_update.into_analog();
|
|
|
|
|
|
|
|
ad9959
|
|
|
|
};
|
|
|
|
|
|
|
|
let io_expander = {
|
|
|
|
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
|
|
|
|
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
|
|
|
|
let i2c1 = device.I2C1.i2c(
|
|
|
|
(scl, sda),
|
|
|
|
100.khz(),
|
|
|
|
ccdr.peripheral.I2C1,
|
|
|
|
&ccdr.clocks,
|
|
|
|
);
|
|
|
|
mcp23017::MCP23017::default(i2c1).unwrap()
|
|
|
|
};
|
|
|
|
|
|
|
|
let spi = {
|
|
|
|
let spi_mosi = gpiod
|
|
|
|
.pd7
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_miso = gpioa
|
|
|
|
.pa6
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
let spi_sck = gpiog
|
|
|
|
.pg11
|
|
|
|
.into_alternate_af5()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
let config = hal::spi::Config::new(hal::spi::Mode {
|
|
|
|
polarity: hal::spi::Polarity::IdleHigh,
|
|
|
|
phase: hal::spi::Phase::CaptureOnSecondTransition,
|
|
|
|
});
|
|
|
|
|
|
|
|
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
|
|
|
|
// line causing a long RC decay.
|
|
|
|
device.SPI1.spi(
|
|
|
|
(spi_sck, spi_miso, spi_mosi),
|
|
|
|
config,
|
|
|
|
5.mhz(),
|
|
|
|
ccdr.peripheral.SPI1,
|
|
|
|
&ccdr.clocks,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
let (adc1, adc2) = {
|
|
|
|
let (mut adc1, mut adc2) = hal::adc::adc12(
|
|
|
|
device.ADC1,
|
|
|
|
device.ADC2,
|
|
|
|
&mut delay,
|
|
|
|
ccdr.peripheral.ADC12,
|
|
|
|
&ccdr.clocks,
|
|
|
|
);
|
|
|
|
|
|
|
|
let adc1 = {
|
|
|
|
adc1.calibrate();
|
|
|
|
adc1.enable()
|
|
|
|
};
|
|
|
|
|
|
|
|
let adc2 = {
|
|
|
|
adc2.calibrate();
|
|
|
|
adc2.enable()
|
|
|
|
};
|
|
|
|
|
|
|
|
(adc1, adc2)
|
|
|
|
};
|
|
|
|
|
|
|
|
let adc1_in_p = gpiof.pf11.into_analog();
|
|
|
|
let adc2_in_p = gpiof.pf14.into_analog();
|
|
|
|
|
|
|
|
let pounder_devices = pounder::PounderDevices::new(
|
|
|
|
io_expander,
|
|
|
|
spi,
|
|
|
|
adc1,
|
|
|
|
adc2,
|
|
|
|
adc1_in_p,
|
|
|
|
adc2_in_p,
|
|
|
|
)
|
|
|
|
.unwrap();
|
|
|
|
|
|
|
|
let dds_output = {
|
|
|
|
let io_update_trigger = {
|
|
|
|
let _io_update = gpiog
|
|
|
|
.pg7
|
|
|
|
.into_alternate_af2()
|
|
|
|
.set_speed(hal::gpio::Speed::VeryHigh);
|
|
|
|
|
|
|
|
// Configure the IO_Update signal for the DDS.
|
|
|
|
let mut hrtimer = pounder::hrtimer::HighResTimerE::new(
|
|
|
|
device.HRTIM_TIME,
|
|
|
|
device.HRTIM_MASTER,
|
|
|
|
device.HRTIM_COMMON,
|
|
|
|
ccdr.clocks,
|
|
|
|
ccdr.peripheral.HRTIM,
|
|
|
|
);
|
|
|
|
|
|
|
|
// IO_Update occurs after a fixed delay from the QSPI write. Note that the timer
|
|
|
|
// is triggered after the QSPI write, which can take approximately 120nS, so
|
|
|
|
// there is additional margin.
|
|
|
|
hrtimer.configure_single_shot(
|
|
|
|
pounder::hrtimer::Channel::Two,
|
|
|
|
design_parameters::POUNDER_IO_UPDATE_DURATION,
|
|
|
|
design_parameters::POUNDER_IO_UPDATE_DELAY,
|
|
|
|
);
|
|
|
|
|
|
|
|
// Ensure that we have enough time for an IO-update every sample.
|
|
|
|
let sample_frequency = {
|
|
|
|
let timer_frequency: hal::time::Hertz =
|
|
|
|
design_parameters::TIMER_FREQUENCY.into();
|
2021-02-04 19:48:25 +08:00
|
|
|
timer_frequency.0 as f32
|
|
|
|
/ design_parameters::ADC_SAMPLE_TICKS as f32
|
2021-01-18 23:47:47 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
let sample_period = 1.0 / sample_frequency;
|
|
|
|
assert!(
|
|
|
|
sample_period > design_parameters::POUNDER_IO_UPDATE_DELAY
|
|
|
|
);
|
|
|
|
|
|
|
|
hrtimer
|
|
|
|
};
|
|
|
|
|
|
|
|
let (qspi, config) = ad9959.freeze();
|
|
|
|
DdsOutput::new(qspi, io_update_trigger, config)
|
|
|
|
};
|
|
|
|
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
|
|
let pounder_stamper = {
|
|
|
|
let etr_pin = gpioa.pa0.into_alternate_af3();
|
|
|
|
|
|
|
|
// The frequency in the constructor is dont-care, as we will modify the period + clock
|
|
|
|
// source manually below.
|
|
|
|
let tim8 =
|
|
|
|
device
|
|
|
|
.TIM8
|
|
|
|
.timer(1.khz(), ccdr.peripheral.TIM8, &ccdr.clocks);
|
|
|
|
let mut timestamp_timer = timers::PounderTimestampTimer::new(tim8);
|
|
|
|
|
|
|
|
// Pounder is configured to generate a 500MHz reference clock, so a 125MHz sync-clock is
|
|
|
|
// output. As a result, dividing the 125MHz sync-clk provides a 31.25MHz tick rate for
|
|
|
|
// the timestamp timer. 31.25MHz corresponds with a 32ns tick rate.
|
2021-02-04 22:42:29 +08:00
|
|
|
// This is less than fCK_INT/3 of the timer as required for oversampling the trigger.
|
2021-01-18 23:47:47 +08:00
|
|
|
timestamp_timer.set_external_clock(timers::Prescaler::Div4);
|
|
|
|
timestamp_timer.start();
|
|
|
|
|
2021-02-04 23:51:34 +08:00
|
|
|
// Set the timer to wrap at the u16 boundary to meet the PLL periodicity.
|
2021-02-04 22:42:29 +08:00
|
|
|
// Scale and wrap before or after the PLL.
|
2021-02-04 23:51:34 +08:00
|
|
|
timestamp_timer.set_period_ticks(u16::MAX);
|
2021-01-18 23:47:47 +08:00
|
|
|
let tim8_channels = timestamp_timer.channels();
|
|
|
|
|
|
|
|
pounder::timestamp::Timestamper::new(
|
|
|
|
timestamp_timer,
|
|
|
|
dma2_streams.0,
|
|
|
|
tim8_channels.ch1,
|
|
|
|
&mut sampling_timer,
|
|
|
|
etr_pin,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
|
|
|
|
Some(PounderDevices {
|
|
|
|
pounder: pounder_devices,
|
|
|
|
dds_output,
|
|
|
|
|
|
|
|
#[cfg(feature = "pounder_v1_1")]
|
|
|
|
timestamper: pounder_stamper,
|
|
|
|
})
|
|
|
|
} else {
|
|
|
|
None
|
|
|
|
};
|
|
|
|
|
2021-01-19 00:23:21 +08:00
|
|
|
let stabilizer = StabilizerDevices {
|
|
|
|
afes,
|
|
|
|
adcs,
|
|
|
|
dacs,
|
|
|
|
timestamper: input_stamper,
|
|
|
|
net: network_devices,
|
|
|
|
adc_dac_timer: sampling_timer,
|
|
|
|
timestamp_timer,
|
2021-02-17 19:08:03 +08:00
|
|
|
cycle_counter: CycleCounter::new(core.DWT, ccdr.clocks.c_ck()),
|
2021-01-19 00:23:21 +08:00
|
|
|
};
|
|
|
|
|
2021-01-18 23:47:47 +08:00
|
|
|
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
|
|
|
|
// info!("Built on {}", build_info::BUILT_TIME_UTC);
|
|
|
|
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
|
|
|
|
|
|
|
|
// Enable the instruction cache.
|
|
|
|
core.SCB.enable_icache();
|
|
|
|
|
|
|
|
(stabilizer, pounder)
|
|
|
|
}
|