2020-11-25 00:09:36 +08:00
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/// The ADC setup time is the number of seconds after the CSn line goes low before the serial clock
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/// may begin. This is used for performing the internal ADC conversion.
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pub const ADC_SETUP_TIME: f32 = 220e-9;
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/// The maximum DAC/ADC serial clock line frequency. This is a hardware limit.
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pub const ADC_DAC_SCK_MHZ_MAX: u32 = 50;
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2020-12-08 21:25:46 +08:00
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/// The optimal counting frequency of the hardware timers used for timestamping and sampling.
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pub const TIMER_FREQUENCY_MHZ: u32 = 100;
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2020-12-15 20:13:05 +08:00
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/// The DDS reference clock frequency in MHz.
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pub const DDS_REF_CLK_MHZ: u32 = 100;
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/// The multiplier used for the DDS reference clock PLL.
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pub const DDS_MULTIPLIER: u8 = 5;
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/// The rate of the DDS SYNC_CLK in MHz is always 1/4 that of the internal PLL clock.
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pub const DDS_SYNC_CLK_MHZ: u32 = DDS_REF_CLK_MHZ * DDS_MULTIPLIER as u32 / 4;
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