f36b1a610e
timer::global: wrap us in Microseconds, impl embedded_hal blocking delay traits
2020-07-22 23:41:15 +02:00
7f45d10af3
timer::global::CountDown: fix delaying from "up to" to "at least" the timespan
2020-07-22 22:43:10 +02:00
855d94c48e
dmac: remove unused module
2020-07-20 19:42:32 +02:00
f8785c3f07
fix some compilation warnings
2020-07-19 15:39:08 +08:00
484e385160
eth: implement DeviceCapabilities.max_burst_size
...
this is a hint that /could/ boost TCP performance.
2020-07-16 00:17:13 +02:00
371e59cef5
libboard_zynq: add fpgax_clk_ctrl registers
2020-07-07 19:37:51 +08:00
e4e7141bf3
ddr: delint
2020-07-06 19:46:18 +02:00
0c60d684e4
slcr: remove soft reset
...
Does not work and probably difficult to get to work.
2020-07-06 13:06:10 +08:00
21c0c5cbc8
Revert "simplify ps7_init"
...
What the simplified ps7_init does can now be reproduced by the DDRC driver.
On the other hand, we are still experiencing crazy Zynq instability issues, so keep the original ps7_init around for debugging.
This reverts commit 9fcf9243f2
2020-07-06 11:55:04 +08:00
90904634cd
DDR: fixed register write.
...
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
2020-07-06 11:46:37 +08:00
9fcf9243f2
simplify ps7_init
2020-07-06 00:52:40 +08:00
f0697c3ec3
ddr: implement additional configuration
2020-07-03 02:20:10 +02:00
b2c707d543
ddr: remove superfluous _reg from register names
2020-07-03 02:20:10 +02:00
c0e66a632c
ps7_init: move from experiments to libboard_zynq
2020-06-25 01:40:42 +02:00
b33ccf83ba
eth: doc
2020-06-18 18:07:50 +02:00
a80a2c67ef
eth: put desc list behind UncachedSlice, invalidate buffers, add barriers
2020-06-18 01:28:29 +02:00
98f5099684
removed newline character
2020-06-16 17:36:01 +08:00
2c3fa991ad
implemented display trait for errors
2020-06-16 17:36:01 +08:00
2c14a2a1a2
fixed global timer reset
2020-06-16 17:31:37 +08:00
191da7c959
Added Copy trait for Milliseconds struct.
2020-06-16 14:56:29 +08:00
d52466cacf
DevC driver refactored.
2020-06-16 14:55:53 +08:00
a17a5d2925
sdcard: Changed some debug to trace.
2020-06-15 16:54:30 +08:00
e0f26871db
devc working!
2020-06-15 16:07:31 +08:00
82ec1ba7a7
sdio: better logging
2020-06-13 16:31:25 +08:00
d3b488bfb3
standard capacity support
2020-06-11 10:21:01 +08:00
074b3547de
sdio: fix unsound MaybeUninit usage
2020-06-11 10:07:19 +08:00
316ea61702
sdio: move ADMA2_DESCR32_TABLE into SdCard
2020-06-11 10:07:19 +08:00
1586190712
sdio: turn Adma2Desc32.attribute into a register!
2020-06-11 10:07:19 +08:00
32349e9dec
sdio: convert Adma2Desc32 to VolatileCells, make ADMA2_DESCR32_TABLE: MaybeUninit
2020-06-11 10:07:19 +08:00
b942cdcbc8
sdio: change Adma2Desc32 alignment from 1 to 4
...
this should not break anything.
2020-06-11 10:07:19 +08:00
a1a211334f
eth: always just allocate desc list + buffers
...
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
2020-06-11 00:21:18 +02:00
cf17a1c60a
removed unneeded methods
2020-06-10 12:55:22 +08:00
5332587de6
Changed mutability
2020-06-10 12:54:50 +08:00
0ebc4a61c8
Modified SDIO to handle u8 buffer instead of u32.
2020-06-09 17:03:17 +08:00
236592ae66
SDIO module completed
2020-06-05 12:27:12 +08:00
2c82fb793e
Merge pull request 'sdio-registers' ( #29 )
2020-05-15 06:44:32 +08:00
0c48dd934e
libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en
2020-05-10 22:14:55 +02:00
3841accd9c
libboard_zynq: fix ddr memtest range
2020-05-09 02:53:58 +02:00
3e02980c20
libboard_zynq: fix access to "full" 1022 MB on target_zc706
2020-05-09 02:35:39 +02:00
73b0ec9837
fixed typo
2020-05-06 13:58:46 +08:00
4acee21c05
Merge branch 'master' of git.m-labs.hk:M-Labs/zc706 into sdio-registers
2020-05-06 11:06:38 +08:00
ce844f1b02
devc: add is_done()
2020-05-04 22:16:53 +08:00
c955eaae7f
libboard_zynq: flush Uart by waiting for tx idle
2020-05-02 23:32:01 +02:00
0f666c570c
libboard_zynq: remove unneeded Uart flush
2020-05-02 23:30:45 +02:00
244ccdeac2
finished register definitions
2020-05-01 15:38:07 +08:00
e047c2900b
ddr: log clock info with debug level
2020-05-01 12:27:43 +08:00
877f2c34bd
libboard_zynq: use log logging
2020-05-01 01:46:42 +02:00
619ebf147c
libsupport_zynq: move mod logger to libboard_zynq
2020-05-01 01:33:40 +02:00
0d4d021b1b
clean up
2020-05-01 01:17:53 +02:00
d9e8a667bd
some macro changes and more registers
2020-04-29 21:19:24 +08:00
