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9d725bcf0f
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zynq::ddr: init with clock setup
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2019-10-21 22:12:10 +02:00 |
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58cf9833cc
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slcr: implement PllCfg and DdrClkCtrl
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2019-10-21 22:10:51 +02:00 |
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83b8bb096a
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add zynq::axi_gp
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2019-10-19 01:46:43 +02:00 |
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b541160f38
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add zynq::axi_hp
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2019-10-18 23:46:00 +02:00 |
|
Björn Stein
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1804c4c6e8
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cortex_a9: add proper L1 cache invalidation
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2019-10-18 00:11:51 +02:00 |
|
Björn Stein
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d87b874b21
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eth: add memory barriers, reorder access
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2019-10-18 00:04:22 +02:00 |
|
Björn Stein
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9053166acc
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eth: increase desc list safety
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2019-10-18 00:03:17 +02:00 |
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4e9c38527e
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rm debug, delint
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2019-09-29 03:01:24 +02:00 |
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a76214cb9d
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eth: split into Eth and EthInner
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2019-09-29 02:58:17 +02:00 |
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0f6bc68d1f
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eth: prepare link change detection
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2019-09-29 02:30:03 +02:00 |
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378755a0ce
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main: bump RX_LEN/TX_LEN to 2
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2019-09-29 01:40:38 +02:00 |
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644cc64524
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eth: align DescEntries
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2019-09-29 01:39:12 +02:00 |
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4c62ce0dad
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main: restrict eth buffers to 1 each
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2019-08-19 02:21:36 +02:00 |
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9c73cf130d
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eth: wait for link
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2019-08-19 02:21:02 +02:00 |
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45ed5f6c5b
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abort handlers: replace panic with infinite loop
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2019-08-19 01:18:12 +02:00 |
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d11e581862
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main: setup smoltcp
still panics, leading to a DataAbort
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2019-08-19 01:18:12 +02:00 |
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|
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3a5ed0aac6
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eth: add smoltcp support
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2019-08-19 01:18:12 +02:00 |
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|
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5603766c5d
|
eth: enable csum offloading
should prevent FCS errors
|
2019-08-19 01:12:52 +02:00 |
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|
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43c3f3e4a6
|
eth: fix tx_clock magnitude bug
Ethernet TX now works!
|
2019-08-18 22:52:05 +02:00 |
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4bc1d21ae9
|
eth: rm obsolete TODO
|
2019-08-18 22:44:33 +02:00 |
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|
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bfb3a00a4e
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eth: derive proper mdc_clk_div from clocks
|
2019-08-18 22:43:56 +02:00 |
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|
|
b8818863c4
|
read clocks
|
2019-08-17 03:20:04 +02:00 |
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|
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1f9ad5ff62
|
delint
|
2019-08-11 00:56:54 +02:00 |
|
|
|
b7690c9702
|
fix UART_REF_CLK
started to become garbled.
|
2019-08-07 00:27:01 +02:00 |
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|
|
d001593a36
|
rm bcmp
|
2019-08-06 22:03:23 +02:00 |
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|
|
2db35d063f
|
define bcmp
other solution might be defining a non-linux target
|
2019-08-06 14:15:44 +02:00 |
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|
|
b9c233b05b
|
compile fixes
|
2019-07-01 00:15:17 +02:00 |
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|
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d6b2321fee
|
eth: fix mio_pin setup
|
2019-06-29 00:00:22 +02:00 |
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|
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9ab40daca2
|
eth: setup_gem0/1_clock()
|
2019-06-25 21:50:38 +02:00 |
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|
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5823d90db1
|
phy: implement control, status, reset
|
2019-06-25 21:48:47 +02:00 |
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|
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e6827a81f3
|
eth tx: set net_ctrl.start_tx on sending
|
2019-06-25 01:46:29 +02:00 |
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|
|
374686fd3e
|
eth tx: set last_buffer flag
|
2019-06-24 02:15:11 +02:00 |
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|
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ce74fe7299
|
eth: prepare tx
|
2019-06-22 01:39:44 +02:00 |
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|
|
ec5dda4d0a
|
eth: add const MTU
|
2019-06-22 01:34:17 +02:00 |
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|
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6757ceb76c
|
eth rx: error handling
|
2019-06-22 01:20:18 +02:00 |
|
|
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a4be03bee9
|
rx: PktRef
|
2019-06-21 01:19:04 +02:00 |
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|
|
80f003b2c6
|
stdio: add print
|
2019-06-21 01:18:24 +02:00 |
|
|
|
e5881a14ad
|
eth rx: descriptors/buffers as refs
avoid moving these after their addresses have been written to the qbar
|
2019-06-21 00:58:18 +02:00 |
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|
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d65398205f
|
add a println! for convenience
|
2019-06-20 00:30:18 +02:00 |
|
|
|
b3b65f9b74
|
eth: find Phy
|
2019-06-19 00:21:17 +02:00 |
|
|
|
54d0f3583d
|
eth: fix io configuration
phy detection now works
|
2019-06-18 23:10:35 +02:00 |
|
|
|
1634513bc7
|
mmu: align l1_table
|
2019-06-18 19:18:47 +02:00 |
|
|
|
9bebfb49bc
|
begin MMU implementation
|
2019-06-17 03:32:10 +02:00 |
|
|
|
69b65b5f72
|
cortex_a9 regs: allow defining bit fields
|
2019-06-17 01:36:11 +02:00 |
|
|
|
1e16beb707
|
cortex_a9::regs: use crate::regs interface
|
2019-06-12 00:20:23 +02:00 |
|
|
|
81a892b618
|
eth: recv_next()
|
2019-06-10 02:44:29 +02:00 |
|
|
|
f92ea3b99d
|
eth: start_tx
|
2019-06-09 20:28:33 +02:00 |
|
|
|
f07a541c99
|
eth: model rx/tx state with type parameters
|
2019-06-09 20:10:41 +02:00 |
|
|
|
74bd81f87f
|
eth: add safety asserts
|
2019-06-09 02:23:37 +02:00 |
|
|
|
824e91e6cb
|
eth: rx/tx desc list, start_rx
|
2019-06-09 01:02:10 +02:00 |
|
