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cae02947bc
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zynq::eth: remove all memory barriers
They were not the solution.
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2019-11-10 23:52:55 +01:00 |
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74c43b3477
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zynq::eth::tx: clear entry.word1 for each packet
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2019-11-04 02:31:40 +01:00 |
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5c62716a99
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zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
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2019-10-31 03:15:13 +01:00 |
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c046bbf8a2
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move slcr, clocks, uart, eth into src/zynq/
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2019-10-21 22:19:03 +02:00 |
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