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mmu: switch bufferable=1 (writeback) for DDR pages

This commit is contained in:
Astro 2020-06-14 23:49:17 +02:00
parent 98f5099684
commit aebce435e2
1 changed files with 1 additions and 1 deletions

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@ -132,7 +132,7 @@ impl L1Table {
domain: 0b1111,
exec: true,
cacheable: true,
bufferable: false,
bufferable: true,
});
}
/* 0x40000000 - 0x7fffffff (FPGA slave0) */