forked from M-Labs/zynq-rs
libboard_zynq: complete ddr without ps7_init for redpitaya
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8fd317d580
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990fa56d6a
@ -1,12 +1,9 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{debug, info, error};
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use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::slcr;
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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#[cfg(feature = "target_redpitaya")]
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use super::ps7_init;
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mod regs;
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#[cfg(feature = "target_zc706")]
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@ -18,8 +15,8 @@ const DDR_FREQ: u32 = 666_666_666;
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const DDR_FREQ: u32 = 525_000_000;
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#[cfg(feature = "target_redpitaya")]
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3
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const DDR_FREQ: u32 = 800_000_000;
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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@ -30,15 +27,6 @@ pub struct DdrRam {
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impl DdrRam {
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pub fn ddrram() -> Self {
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if cfg!(feature = "target_redpitaya") {
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// We have not yet fixed red pitaya initialization yet. It seems
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// that the clock configuration, iob settings and ddr settings are
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// all problematic
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#[cfg(feature = "target_redpitaya")]
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ps7_init::apply();
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let regs = regs::RegisterBlock::ddrc();
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DdrRam { regs }
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} else {
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let clocks = Self::clock_setup();
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Self::configure_iob();
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Self::calibrate_iob_impedance(&clocks);
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@ -47,7 +35,6 @@ impl DdrRam {
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ddr.reset_ddrc(|ddr| ddr.configure());
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ddr
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}
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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@ -237,6 +224,7 @@ impl DdrRam {
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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.refio_en(true)
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);
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});
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}
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@ -249,6 +237,13 @@ impl DdrRam {
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.t_rfc_min(0x9e)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1b)
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.t_rfc_min(0xa0)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_zc706")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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@ -256,6 +251,16 @@ impl DdrRam {
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.t_rfc_min(0x56)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param1.modify(
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|_, w| w
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.wr2pre(0x12)
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.powerdown_to_x32(6)
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.t_faw(0x16)
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.t_ras_max(0x24)
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.t_ras_min(0x13)
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.t_cke(4)
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);
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self.regs.dram_param2.write(
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regs::DramParam2::zeroed()
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@ -267,6 +272,20 @@ impl DdrRam {
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.rd2pre(0x4)
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.t_rcd(0x7)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param3.modify(
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|_, w| w
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.t_ccd(4)
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.t_rrd(6)
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.refresh_margin(2)
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.t_rp(7)
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.refresh_to_x32(8)
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.mobile(false)
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.dfi_dram_clk_disable(false)
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.read_latency(7)
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.mode_ddr1_ddr2(true)
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.dis_pad_pd(false)
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);
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self.regs.dram_emr_mr.write(
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regs::DramEmrMr::zeroed()
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@ -275,11 +294,19 @@ impl DdrRam {
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config2.modify(
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config3.modify(
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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);
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@ -316,7 +343,7 @@ impl DdrRam {
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);
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#[cfg(feature = "target_zc706")]
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self.regs.phy_init_ratio3.write(
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self.regs.phy_init_ratios[3].write(
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regs::PhyInitRatio::zeroed()
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.wrlvl_init_ratio(0x21)
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.gatelvl_init_ratio(0xee)
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@ -328,6 +355,18 @@ impl DdrRam {
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.phy_ctrl_slave_ratio(0x100)
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.phy_invert_clkout(true)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.reg_64.modify(
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|_, w| w
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.phy_bl2(false)
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.phy_invert_clkout(true)
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.phy_sel_logic(false)
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.phy_ctrl_slave_ratio(0x100)
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.phy_ctrl_slave_force(false)
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.phy_ctrl_slave_delay(0)
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.phy_lpddr(false)
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.phy_cmd_latency(false)
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);
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self.regs.reg_65.write(
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regs::Reg65::zeroed()
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@ -364,7 +403,7 @@ impl DdrRam {
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000666);
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@ -60,7 +60,7 @@ pub struct RegisterBlock {
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pub ctrl6: RW<u32>,
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_unused1: [RO<u32>; 8],
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pub che_refresh_timer01: RW<u32>,
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pub che_t_zq: RW<u32>,
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pub che_t_zq: CheTZq,
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pub che_t_zq_short_interval: RW<u32>,
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pub deep_pwrdwn: RW<u32>,
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pub reg_2c: Reg2C,
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@ -84,15 +84,9 @@ pub struct RegisterBlock {
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pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
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_unused3: [RO<u32>; 5],
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pub phy_rcvr_enable: RW<u32>,
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pub phy_config0: PhyConfig,
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pub phy_config1: PhyConfig,
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pub phy_config2: PhyConfig,
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pub phy_config3: PhyConfig,
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pub phy_configs: [PhyConfig; 4],
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_unused4: RO<u32>,
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pub phy_init_ratio0: PhyInitRatio,
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pub phy_init_ratio1: PhyInitRatio,
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pub phy_init_ratio2: PhyInitRatio,
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pub phy_init_ratio3: PhyInitRatio,
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pub phy_init_ratios: [PhyInitRatio; 4],
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_unused5: RO<u32>,
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pub phy_rd_dqs_cfg0: RW<u32>,
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pub phy_rd_dqs_cfg1: RW<u32>,
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@ -138,10 +132,7 @@ pub struct RegisterBlock {
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_unused14: [RO<u32>; 5],
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pub axi_id: RW<u32>,
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pub page_mask: RW<u32>,
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pub axi_priority_wr_port0: RW<u32>,
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pub axi_priority_wr_port1: RW<u32>,
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pub axi_priority_wr_port2: RW<u32>,
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pub axi_priority_wr_port3: RW<u32>,
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pub axi_priority_wr_ports: [RW<u32>; 4],
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pub axi_priority_rd_ports: [AxiPriorityRd; 4],
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_unused15: [RO<u32>; 27],
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pub excl_access_cfg0: RW<u32>,
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@ -222,6 +213,13 @@ register_bit!(phy_cmd_timeout_rddata_cpt, clk_stall_level, 19);
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register_bits!(phy_cmd_timeout_rddata_cpt, gatelvl_num_of_dq0, u8, 24, 27);
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register_bits!(phy_cmd_timeout_rddata_cpt, wrlvl_num_of_dq0, u8, 28, 31);
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register!(che_t_zq, CheTZq, RW, u32);
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register_bit!(che_t_zq, dis_auto_zq, 0);
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register_bit!(che_t_zq, ddr3, 1);
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register_bits!(che_t_zq, t_mod, u8, 2, 11);
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register_bits!(che_t_zq, t_zq_long_nop, u16, 12, 21);
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register_bits!(che_t_zq, t_zq_short_nop, u16, 22, 31);
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register!(reg_2c, Reg2C, RW, u32);
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register_bits!(reg_2c, wrlvl_max_x1024, u16, 0, 11);
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register_bits!(reg_2c, rdlvl_max_x1024, u16, 12, 23);
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