2020-09-29 16:27:44 +08:00
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# Bare-metal Rust on Zynq-7000
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Supported features:
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* Clocking setup
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* UART
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* SDRAM setup
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* Ethernet with smoltcp and async-await on TCP sockets
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* SD card
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* PL programming and startup
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* Pure Rust SZL first-stage bootloader, with SD boot and netboot
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* Control of second CPU core and message passing, with async-await support
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Supported boards:
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* ZC706
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* Red Pitaya (note: SDRAM issues, worked around using `ps7_init`)
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* Cora Z7-10 (note: SDRAM issues)
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## Build
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2019-05-25 08:38:05 +08:00
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```shell
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2020-08-11 11:24:21 +08:00
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nix-shell --command "cargo xbuild --release -p experiments"
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2019-05-25 08:38:05 +08:00
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```
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2020-01-26 08:45:02 +08:00
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Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments`
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2020-01-24 07:04:16 +08:00
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2020-09-29 16:27:44 +08:00
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## Debug
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2019-05-20 07:21:48 +08:00
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2020-09-29 16:27:44 +08:00
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### Running on the ZC706
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2019-05-25 08:38:05 +08:00
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2019-06-29 08:41:36 +08:00
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```shell
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2020-08-11 11:24:21 +08:00
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nix-shell --command "cargo xbuild --release -p experiments"
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2019-08-20 13:45:50 +08:00
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cd openocd
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openocd -f zc706.cfg
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2019-06-29 08:41:36 +08:00
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```
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2019-05-25 08:38:05 +08:00
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2020-09-29 16:27:44 +08:00
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### Running on the Cora Z7-10
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2019-05-25 08:38:05 +08:00
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```shell
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2020-11-14 00:56:47 +08:00
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nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
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2019-08-20 13:45:50 +08:00
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cd openocd
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openocd -f cora-z7-10.cfg
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2019-05-25 08:38:05 +08:00
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```
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2020-01-15 05:07:19 +08:00
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2020-09-29 16:27:44 +08:00
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### Loading a bitstream into volatile memory
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2020-01-16 02:14:16 +08:00
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```shell
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2020-08-11 11:24:21 +08:00
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openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"
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2020-01-16 02:14:16 +08:00
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```
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