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zynq-rs/openocd/zynq-7000.cfg

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#
# Xilinx Zynq 7000 SoC
#
# Chris Johns <chrisj@rtems.org>
#
# Setup
# -----
#
# Create a user configuration following the "Configuration Basics" in the user
# documentation. In the file have:
#
# source [find interface/ftdi/flyswatter2.cfg]
# source [find board/zynq-zc706-eval.cfg]
# adapter_khz 2000
# init
#
if { [info exists CHIPNAME] } {
global _CHIPNAME
set _CHIPNAME $CHIPNAME
} else {
global _CHIPNAME
set _CHIPNAME zynq
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a bigendian
set _ENDIAN little
}
if { [info exists SMP] } {
global _SMP
set _SMP 1
} else {
global _SMP
set _SMP 0
}
#
# PL Tap.
#
# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
# 0x03731093 - ZC706 Eval board 1.1
# 0x23731093 - ??
# 0x23727093 - Zedboard Rev. C and D
#
# Set in your configuration file or board specific file.
#
if { [info exists PL_TAPID] } {
set _PL_TAPID $PL_TAPID
} else {
set _PL_TAPID 0x03731093
}
jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
-expected-id $_PL_TAPID
#
# CoreSight Debug Access Port
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
-expected-id $_DAP_TAPID
#
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0xF8890000
# core 1 - 0xF8892000
#
# Read from the ROM table with the patch to read the nested table.
#
set _TARGETNAME_0 $_CHIPNAME.cpu.0
set _TARGETNAME_1 $_CHIPNAME.cpu.1
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
target create $_TARGETNAME_0 cortex_a -coreid 0 \
-endian $_ENDIAN \
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-dap $_CHIPNAME.dap \
-dbgbase 0x80090000
if { $_SMP } {
echo "Zynq CPU1."
target create $_TARGETNAME_1 cortex_a -coreid 1 \
-endian $_ENDIAN \
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-dap $_CHIPNAME.dap \
-dbgbase 0x80092000
target smp $_TARGETNAME_0 $_TARGETNAME_1
}