forked from M-Labs/artiq-zynq
zc706: added dummy spi in place of sdio
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3096daaaee
commit
21eb1cab1a
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@ -93,10 +93,7 @@ pmod1_33 = [
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("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
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("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
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("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
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("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
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("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
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("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
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("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
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# rest removed for use with dummy spi
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("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
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("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
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("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
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]
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]
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_ams101_dac = [
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_ams101_dac = [
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@ -109,6 +106,17 @@ _ams101_dac = [
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)
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)
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]
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]
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_dummy_spi = [
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("dummy_spi", 0,
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# PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
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Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
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Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
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Subsignal("mosi", Pins("AC18"), IOStandard("LVCMOS25")),
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Subsignal("cs_n", Pins("AC19"), IOStandard("LVCMOS25")),
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IOStandard("LVCMOS25")
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)
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]
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def prepare_zc706_platform(platform):
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def prepare_zc706_platform(platform):
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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@ -459,6 +467,7 @@ class _NIST_CLOCK_RTIO:
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platform.add_extension(leds_fmc33)
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platform.add_extension(leds_fmc33)
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platform.add_extension(pmod1_33)
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platform.add_extension(pmod1_33)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_dummy_spi)
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rtio_channels = []
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rtio_channels = []
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@ -506,10 +515,10 @@ class _NIST_CLOCK_RTIO:
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rtio_channels.append(rtio.Channel.from_phy(
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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phy, ififo_depth=128))
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# no SDIO on PL side, PMOD1_1 placeholder instead
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# no SDIO on PL side, dummy SPI placeholder instead
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 1))
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phy = spi2.SPIMaster(platform.request("dummy_spi"))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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self.submodules += phy
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