forked from M-Labs/artiq-zynq
zc706: removed nist_clock sdcard, put pmod instead
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4fbfccf575
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3096daaaee
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@ -109,15 +109,6 @@ _ams101_dac = [
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)
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]
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_sdcard_spi_33 = [
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")),
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Subsignal("clk", Pins("B20")),
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Subsignal("mosi", Pins("J18")),
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Subsignal("cs_n", Pins("H18")),
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IOStandard("LVCMOS33")
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)
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]
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def prepare_zc706_platform(platform):
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platform.toolchain.bitstream_commands.extend([
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@ -468,7 +459,6 @@ class _NIST_CLOCK_RTIO:
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platform.add_extension(leds_fmc33)
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platform.add_extension(pmod1_33)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_sdcard_spi_33)
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rtio_channels = []
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@ -516,10 +506,10 @@ class _NIST_CLOCK_RTIO:
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
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# no SDIO on PL side, PMOD1_1 placeholder instead
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 1))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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