Harry Ho
64e85fc143
* A single `SyncDDSTTL` experiment definition can be used to test DAC and TTL outputs. * For ST1/ST3, simply run this on Sayma gateware that produces hardcoded waves at SAWGs. * For ST2/ST4, either: * simply run this on Sayma gateware that produces hardcoded waves at both SAWGs and TTLs; or * set `gen_ttl_wave=true` and run this on Sayma gateware that produces hardcoded waves at SAWGs only, while both MCXs are used as TTLOuts.
109 lines
3.2 KiB
Python
109 lines
3.2 KiB
Python
core_addr = "localhost"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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}
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}
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# master peripherals
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# * None is needed.
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"""
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$ artiq_route metlino_routing.bin show
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0: 0
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1: 2 0
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2: 2 1 0
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3: 4 0
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4: 4 1 0
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"""
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# DEST#1/2, #3/4 peripherals
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for sayma in range(2):
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amc_base = (sayma*0x020000) + 0x010000
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rtm_base = (sayma*0x020000) + 0x020000
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# MCX TTLs on Sayma AMC
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for i in range(2):
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device_db["ttl" + str(sayma*2+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": amc_base + 4+i},
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}
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# Example on Sayma#1 RTM
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# BaseMod0 RF switches starting at RTIO channel 0x000000
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# BaseMod0 attenuator starting at RTIO channel 0x000004
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# BaseMod1 RF switches starting at RTIO channel 0x000009
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# BaseMod1 attenuator starting at RTIO channel 0x00000d
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for basemod in range(2):
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for i in range(4):
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device_db["sawg_sw" + str(8*sayma + 4*basemod+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + i}
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}
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att_idx = 2*sayma + basemod
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device_db["basemod_att_rst_n"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 4}
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}
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device_db["basemod_att_clk"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 5}
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}
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device_db["basemod_att_le"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 6}
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}
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device_db["basemod_att_mosi"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 7}
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}
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device_db["basemod_att_miso"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": rtm_base + basemod*9 + 8}
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}
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device_db["basemod_att"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.basemod_att",
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"class": "BaseModAtt",
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"arguments": {
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"rst_n": "basemod_att_rst_n"+str(att_idx),
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"clk": "basemod_att_clk"+str(att_idx),
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"le": "basemod_att_le"+str(att_idx),
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"mosi": "basemod_att_mosi"+str(att_idx),
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"miso": "basemod_att_miso"+str(att_idx),
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}
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} |