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ad7172: rename reg bit bi_unipolar to bipolar

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Astro 2019-09-16 23:28:28 +02:00
parent ee4d24de6a
commit d4428b7fdc
2 changed files with 2 additions and 2 deletions
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2
firmware/src/ad7172/adc.rs
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@ -45,7 +45,7 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
&mut self, index: u8, in_pos: Input, in_neg: Input &mut self, index: u8, in_pos: Input, in_neg: Input
) -> Result<(), AdcError<SPI::Error>> { ) -> Result<(), AdcError<SPI::Error>> {
self.update_reg(&regs::SetupCon { index }, |data| { self.update_reg(&regs::SetupCon { index }, |data| {
data.set_bi_unipolar(false); data.set_bipolar(false);
})?; })?;
self.update_reg(&regs::FiltCon { index }, |data| { self.update_reg(&regs::FiltCon { index }, |data| {
// 10 Hz data rate // 10 Hz data rate

2
firmware/src/ad7172/regs.rs
View File

@ -198,7 +198,7 @@ impl channel::Data {
def_reg!(SetupCon, u8, setup_con, 0x20, 2); def_reg!(SetupCon, u8, setup_con, 0x20, 2);
impl setup_con::Data { impl setup_con::Data {
reg_bit!(bi_unipolar, set_bi_unipolar, 0, 6, "Unipolar (`false`) or bipolar (`true`) coded output"); reg_bit!(bipolar, set_bipolar, 0, 6, "Unipolar (`false`) or bipolar (`true`) coded output");
reg_bit!(refbuf_pos, set_refbuf_pos, 0, 5, "Enable REF+ input buffer"); reg_bit!(refbuf_pos, set_refbuf_pos, 0, 5, "Enable REF+ input buffer");
reg_bit!(refbuf_neg, set_refbuf_neg, 0, 5, "Enable REF- input buffer"); reg_bit!(refbuf_neg, set_refbuf_neg, 0, 5, "Enable REF- input buffer");
reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 3, "Enable AIN+ input buffer"); reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 3, "Enable AIN+ input buffer");