diff --git a/firmware/src/ad7172/adc.rs b/firmware/src/ad7172/adc.rs
index 52984ce..96672bd 100644
--- a/firmware/src/ad7172/adc.rs
+++ b/firmware/src/ad7172/adc.rs
@@ -45,7 +45,7 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
         &mut self, index: u8, in_pos: Input, in_neg: Input
     ) -> Result<(), AdcError<SPI::Error>> {
         self.update_reg(&regs::SetupCon { index }, |data| {
-            data.set_bi_unipolar(false);
+            data.set_bipolar(false);
         })?;
         self.update_reg(&regs::FiltCon { index }, |data| {
             // 10 Hz data rate
diff --git a/firmware/src/ad7172/regs.rs b/firmware/src/ad7172/regs.rs
index be88516..24bd069 100644
--- a/firmware/src/ad7172/regs.rs
+++ b/firmware/src/ad7172/regs.rs
@@ -198,7 +198,7 @@ impl channel::Data {
 
 def_reg!(SetupCon, u8, setup_con, 0x20, 2);
 impl setup_con::Data {
-    reg_bit!(bi_unipolar, set_bi_unipolar, 0, 6, "Unipolar (`false`) or bipolar (`true`) coded output");
+    reg_bit!(bipolar, set_bipolar, 0, 6, "Unipolar (`false`) or bipolar (`true`) coded output");
     reg_bit!(refbuf_pos, set_refbuf_pos, 0, 5, "Enable REF+ input buffer");
     reg_bit!(refbuf_neg, set_refbuf_neg, 0, 5, "Enable REF- input buffer");
     reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 3, "Enable AIN+ input buffer");