forked from M-Labs/ionpak-thermostat
board: reset timers for clean initialization
raced into hardfaults without.
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9c0f560367
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@ -105,13 +105,34 @@ pub fn init() {
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.pmc7().bits(3)
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});
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// Timers
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// Enable timers
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sysctl.rcgctimer.write(|w| w
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.r2().set_bit()
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.r3().set_bit()
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.r4().set_bit()
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.r5().set_bit()
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);
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// Reset timers
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sysctl.srtimer.write(|w| w
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.r2().set_bit()
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.r3().set_bit()
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.r4().set_bit()
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.r5().set_bit()
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);
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sysctl.srtimer.write(|w| w
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.r2().clear_bit()
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.r3().clear_bit()
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.r4().clear_bit()
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.r5().clear_bit()
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);
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fn timers_ready(sysctl: &tm4c129x::sysctl::RegisterBlock) -> bool {
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let prtimer = sysctl.prtimer.read();
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prtimer.r2().bit() &&
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prtimer.r3().bit() &&
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prtimer.r4().bit() &&
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prtimer.r5().bit()
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}
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while !timers_ready(sysctl) {}
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// Manual: 13.4.5 PWM Mode
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macro_rules! setup_timer_pwm {
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