From 0eefebf3ed97a15c71f40a7705a3a24f6bddae1a Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Thu, 29 Aug 2019 22:39:08 +0200
Subject: [PATCH] board: reset timers for clean initialization

raced into hardfaults without.
---
 firmware/src/board/mod.rs | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/firmware/src/board/mod.rs b/firmware/src/board/mod.rs
index 6af50ee..c510c32 100644
--- a/firmware/src/board/mod.rs
+++ b/firmware/src/board/mod.rs
@@ -105,13 +105,34 @@ pub fn init() {
                 .pmc7().bits(3)
         });
 
-        // Timers
+        // Enable timers
         sysctl.rcgctimer.write(|w| w
             .r2().set_bit()
             .r3().set_bit()
             .r4().set_bit()
             .r5().set_bit()
         );
+        // Reset timers
+        sysctl.srtimer.write(|w| w
+            .r2().set_bit()
+            .r3().set_bit()
+            .r4().set_bit()
+            .r5().set_bit()
+        );
+        sysctl.srtimer.write(|w| w
+            .r2().clear_bit()
+            .r3().clear_bit()
+            .r4().clear_bit()
+            .r5().clear_bit()
+        );
+        fn timers_ready(sysctl: &tm4c129x::sysctl::RegisterBlock) -> bool {
+            let prtimer = sysctl.prtimer.read();
+            prtimer.r2().bit() &&
+                prtimer.r3().bit() &&
+                prtimer.r4().bit() &&
+                prtimer.r5().bit()
+        }
+        while !timers_ready(sysctl) {}
 
         // Manual: 13.4.5 PWM Mode
         macro_rules! setup_timer_pwm {