2017-05-09 15:57:54 +08:00
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#![feature(used, const_fn, core_float)]
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2017-05-04 17:35:26 +08:00
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#![no_std]
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#[macro_use]
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extern crate cortex_m;
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extern crate cortex_m_rt;
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extern crate tm4c129x;
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2017-05-06 17:17:41 +08:00
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use core::cell::{Cell, RefCell};
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2017-05-09 13:16:00 +08:00
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use core::fmt;
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2017-05-04 17:35:26 +08:00
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use cortex_m::ctxt::Local;
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use cortex_m::exception::Handlers as ExceptionHandlers;
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2017-05-06 17:17:41 +08:00
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use cortex_m::interrupt::Mutex;
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2017-05-05 19:31:12 +08:00
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use tm4c129x::interrupt::Interrupt;
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2017-05-04 17:35:26 +08:00
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use tm4c129x::interrupt::Handlers as InterruptHandlers;
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2017-05-09 15:57:54 +08:00
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mod board;
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2017-05-06 17:17:41 +08:00
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mod pid;
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2017-05-09 15:57:54 +08:00
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mod loop_anode;
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mod loop_cathode;
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2017-05-06 17:17:41 +08:00
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2017-05-09 15:57:54 +08:00
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static LOOP_ANODE: Mutex<RefCell<loop_anode::Controller>> = Mutex::new(RefCell::new(
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loop_anode::Controller::new()));
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2017-05-06 12:32:13 +08:00
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2017-05-09 15:57:54 +08:00
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static LOOP_CATHODE: Mutex<RefCell<loop_cathode::Controller>> = Mutex::new(RefCell::new(
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loop_cathode::Controller::new()));
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2017-05-09 13:16:00 +08:00
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pub struct UART0;
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impl fmt::Write for UART0 {
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fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> {
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for c in s.bytes() {
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unsafe {
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let uart_0 = tm4c129x::UART0.get();
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while (*uart_0).fr.read().txff().bit() {}
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(*uart_0).dr.write(|w| w.data().bits(c))
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}
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}
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Ok(())
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}
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}
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#[macro_export]
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macro_rules! print {
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($($arg:tt)*) => ({
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use core::fmt::Write;
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write!($crate::UART0, $($arg)*).unwrap()
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})
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}
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#[macro_export]
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macro_rules! println {
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($fmt:expr) => (print!(concat!($fmt, "\n")));
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($fmt:expr, $($arg:tt)*) => (print!(concat!($fmt, "\n"), $($arg)*));
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}
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2017-05-06 17:17:41 +08:00
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2017-05-04 17:35:26 +08:00
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fn main() {
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2017-05-09 15:57:54 +08:00
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board::init();
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2017-05-04 19:42:22 +08:00
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2017-05-09 15:57:54 +08:00
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cortex_m::interrupt::free(|cs| {
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2017-05-08 01:32:53 +08:00
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// Enable FPU
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let scb = tm4c129x::SCB.borrow(cs);
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scb.enable_fpu();
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2017-05-09 15:57:54 +08:00
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let nvic = tm4c129x::NVIC.borrow(cs);
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2017-05-05 19:31:12 +08:00
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nvic.enable(Interrupt::ADC0SS0);
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2017-05-09 15:57:54 +08:00
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board::set_emission_range(board::EmissionRange::High);
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LOOP_ANODE.borrow(cs).borrow_mut().set_target(30.0+12.0);
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//set_fv_pwm(10);
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board::set_fbv_pwm(20);
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2017-05-04 17:35:26 +08:00
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});
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2017-05-06 12:33:38 +08:00
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2017-05-09 13:16:00 +08:00
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println!("ready");
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2017-05-06 12:33:38 +08:00
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loop {
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2017-05-09 15:57:54 +08:00
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board::process_errors();
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2017-05-06 12:33:38 +08:00
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}
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2017-05-04 17:35:26 +08:00
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}
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2017-05-09 15:57:54 +08:00
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use tm4c129x::interrupt::ADC0SS0;
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extern fn adc0_ss0(ctxt: ADC0SS0) {
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static ELAPSED: Local<Cell<u32>, ADC0SS0> = Local::new(Cell::new(0));
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2017-05-04 17:35:26 +08:00
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let elapsed = ELAPSED.borrow(&ctxt);
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2017-05-05 19:31:12 +08:00
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cortex_m::interrupt::free(|cs| {
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let adc0 = tm4c129x::ADC0.borrow(cs);
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if adc0.ostat.read().ov0().bit() {
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panic!("ADC FIFO overflowed")
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}
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2017-05-07 00:00:01 +08:00
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adc0.isc.write(|w| w.in0().bit(true));
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2017-05-05 19:31:12 +08:00
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2017-05-09 15:57:54 +08:00
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let _ic_sample = adc0.ssfifo0.read().data().bits();
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let fbi_sample = adc0.ssfifo0.read().data().bits();
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let fv_sample = adc0.ssfifo0.read().data().bits();
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let fd_sample = adc0.ssfifo0.read().data().bits();
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let av_sample = adc0.ssfifo0.read().data().bits();
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let fbv_sample = adc0.ssfifo0.read().data().bits();
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let mut loop_anode = LOOP_ANODE.borrow(cs).borrow_mut();
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let mut loop_cathode = LOOP_CATHODE.borrow(cs).borrow_mut();
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loop_anode.adc_input(av_sample);
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loop_cathode.adc_input(fbi_sample, fd_sample, fv_sample, fbv_sample);
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if elapsed.get() % 100 == 0 {
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board::set_led(1, true);
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board::set_led(2, false);
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}
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if elapsed.get() % 100 == 50 {
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board::set_led(1, false);
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board::set_led(2, true);
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}
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2017-05-05 19:31:12 +08:00
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})
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}
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2017-05-04 17:35:26 +08:00
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#[used]
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#[link_section = ".rodata.exceptions"]
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pub static EXCEPTIONS: ExceptionHandlers = ExceptionHandlers {
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..cortex_m::exception::DEFAULT_HANDLERS
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};
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#[used]
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#[link_section = ".rodata.interrupts"]
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pub static INTERRUPTS: InterruptHandlers = InterruptHandlers {
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2017-05-05 19:31:12 +08:00
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ADC0SS0: adc0_ss0,
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2017-05-04 17:35:26 +08:00
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..tm4c129x::interrupt::DEFAULT_HANDLERS
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};
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