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zynq-rs
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Bare-metal Rust on the Xilinx Zynq ZC706 devkit
5 Commits 14 Branches 0 Tags 1.3 MiB
Rust 91.8%
Tcl 5.9%
HAProxy 1.1%
Nix 0.5%
Shell 0.4%
Other 0.2%
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Astro ca9b10dce8 refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
.cargo PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
src refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
Cargo.lock PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
Cargo.toml PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
build.rs PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
default.nix PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
link.x PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
qemu.gdb PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
runner.sh PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00
shell.nix PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00