forked from M-Labs/zynq-rs
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5 Commits
Author | SHA1 | Date |
---|---|---|
Astro | 18f8060a39 | |
Astro | 53eebce39c | |
Astro | 668e3e32ba | |
Astro | ea574a18d8 | |
Astro | 6cb29022df |
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@ -20,8 +20,10 @@ static mut STACK_CORE1: [u32; 512] = [0; 512];
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#[no_mangle]
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#[no_mangle]
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pub fn main_core0() {
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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// zynq::clocks::Clocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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println!("\nzc706 main");
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let clocks = zynq::clocks::Clocks::get();
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println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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{
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{
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use libregister::RegisterR;
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use libregister::RegisterR;
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println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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@ -52,17 +54,36 @@ pub fn main_core0() {
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}
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}
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let mut flash = flash.stop();
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let mut flash = flash.stop();
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let mut ddr = zynq::ddr::DdrRam::new();
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for i in 0../*=*/1 {
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#[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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let mut flash_io = flash.manual_mode(i);
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// println!("rdcr={:02X}", flash_io.rdcr());
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let mut cr: zynq::flash::CR = flash_io.read_reg();
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println!("rdcr={:02X}", cr.inner);
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// if cr.quad() {
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// println!("disabling quad mode...");
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// cr.set_quad(false);
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// let sr1: zynq::flash::SR1 = flash_io.read_reg();
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// println!("sr1={:02X}", sr1.inner);
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// flash_io.write_regs(sr1, cr);
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// }
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// if ! cr.quad() {
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// println!("setting quad mode...");
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// cr.set_quad(true);
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// let sr1: zynq::flash::SR1 = flash_io.read_reg();
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// // println!("sr1={:02X}", sr1.inner);
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// flash_io.write_regs(sr1, cr);
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// }
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print!("Flash {} ID:", i);
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print!("Flash {} ID:", i);
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for b in flash_io.rdid() {
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for (i, b) in flash_io.rdid().enumerate() {
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print!(" {:02X}", b);
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print!(" {:02X}", b);
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if i % 0x10 == 0xf {
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println!("");
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} else if i % 8 == 7 {
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print!(" ");
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} else if i % 4 == 3 {
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print!(" ");
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}
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}
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}
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println!("");
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println!("");
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print!("Flash {} I/O:", i);
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print!("Flash {} I/O:", i);
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@ -85,12 +106,28 @@ pub fn main_core0() {
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flash_io.dump("ASP Read", 0x2B);
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flash_io.dump("ASP Read", 0x2B);
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flash_io.dump("Password Read", 0xE7);
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flash_io.dump("Password Read", 0xE7);
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flash_io.write_enabled(|flash_io| {
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for o in 0..8 {
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flash_io.erase(0);
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const SIZE: u32 = 0x100;
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});
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println!("WREN");
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flash_io.write_enabled(|flash_io| {
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flash_io.write_enabled(|flash_io| {
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flash_io.program(0, [0x23054223; (0x100 >> 2)].iter().cloned());
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println!("Erase page {}", o);
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});
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flash_io.erase(o * SIZE);
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});
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println!("WREN");
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flash_io.write_enabled(|flash_io| {
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println!("Program page {}", o);
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flash_io.program(o * SIZE, [0x26121984; (SIZE >> 2) as usize].iter().cloned());
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});
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}
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print!("Flash {} I/O:", i);
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for o in 0..8 {
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const CHUNK: u32 = 32;
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for b in flash_io.read(CHUNK * o, CHUNK as usize) {
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print!(" {:02X}", b);
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}
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}
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println!("");
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flash = flash_io.stop();
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flash = flash_io.stop();
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}
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}
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@ -119,6 +156,11 @@ pub fn main_core0() {
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}
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}
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println!(".");
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println!(".");
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let mut ddr = zynq::ddr::DdrRam::new();
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// #[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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println!("Eth on");
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@ -172,9 +172,14 @@ impl DdrRam {
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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let width = regs::DataBusWidth::Width16bit;
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let width = regs::DataBusWidth::Width16bit;
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self.regs.ddrc_ctrl.modify(|_, w| w
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.soft_rstb(false)
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.powerdown_en(false)
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.powerdown_en(false)
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.data_bus_width(width)
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.data_bus_width(width)
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.burst8_refresh(1)
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.rdwr_idle_gap(1)
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.dis_rd_bypass(false)
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.dis_act_bypass(false)
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.dis_auto_refresh(false)
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);
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);
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while self.status() == regs::ControllerStatus::Init {}
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while self.status() == regs::ControllerStatus::Init {}
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@ -1,6 +1,6 @@
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use volatile_register::{RO, RW};
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use volatile_register::{RO, RW};
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use libregister::{register, register_bit, register_bits_typed};
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use libregister::{register, register_bit, register_bits, register_bits_typed};
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#[allow(unused)]
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#[allow(unused)]
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#[repr(u8)]
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#[repr(u8)]
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@ -169,7 +169,11 @@ register_bit!(ddrc_ctrl,
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soft_rstb, 0);
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soft_rstb, 0);
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register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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// (ddrc_ctrl) ...
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register_bits!(ddrc_ctrl, burst8_refresh, u8, 4, 6);
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register_bits!(ddrc_ctrl, rdwr_idle_gap, u8, 7, 13);
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register_bit!(ddrc_ctrl, dis_rd_bypass, 14);
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register_bit!(ddrc_ctrl, dis_act_bypass, 15);
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register_bit!(ddrc_ctrl, dis_auto_refresh, 16);
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// Controller operation mode status
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// Controller operation mode status
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register!(mode_sts_reg,
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register!(mode_sts_reg,
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@ -10,16 +10,21 @@ mod regs;
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mod bytes;
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mod bytes;
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pub use bytes::{BytesTransferExt, BytesTransfer};
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pub use bytes::{BytesTransferExt, BytesTransfer};
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mod spi_flash_register;
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mod spi_flash_register;
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use spi_flash_register::*;
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pub use spi_flash_register::*;
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mod transfer;
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mod transfer;
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use transfer::Transfer;
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use transfer::Transfer;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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#[cfg(feature = "target_zc706")]
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const FLASH_BAUD_RATE: u32 = 10_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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const FLASH_BAUD_RATE: u32 = 10_000_000;
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/// 16 MB
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/// 16 MB
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pub const SINGLE_CAPACITY: u32 = 0x1000000;
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pub const SINGLE_CAPACITY: u32 = 0x1000000;
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pub const SECTOR_SIZE: u32 = 0x10000;
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pub const SECTOR_SIZE: u32 = 0x10000;
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pub const PAGE_SIZE: u32 = 0x100;
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pub const PAGE_SIZE: u32 = 0x100;
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/// Write Register
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const INST_WRR: u8 = 0x01;
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/// Instruction: Read Identification
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/// Instruction: Read Identification
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const INST_RDID: u8 = 0x9F;
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const INST_RDID: u8 = 0x9F;
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const INST_READ: u8 = 0x03;
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const INST_READ: u8 = 0x03;
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@ -33,8 +38,10 @@ const INST_PP: u8 = 0x02;
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const INST_SE: u8 = 0xD8;
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const INST_SE: u8 = 0xD8;
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/// Instruction: Erase 4K Block
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/// Instruction: Erase 4K Block
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const INST_BE_4K: u8 = 0x20;
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const INST_BE_4K: u8 = 0x20;
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/// Instruction: Clear Status Register
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const INST_CLSR: u8 = 0x30;
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#[derive(Clone)]
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#[derive(Clone, Debug)]
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pub enum SpiWord {
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pub enum SpiWord {
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W8(u8),
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W8(u8),
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W16(u16),
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W16(u16),
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@ -119,9 +126,11 @@ impl<MODE> Flash<MODE> {
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);
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);
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}
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}
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fn wait_tx_fifo_flush(&mut self) {
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fn wait_tx_fifo_flush(&mut self) -> u32 {
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self.regs.config.modify(|_, w| w.man_start_com(true));
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self.regs.config.modify(|_, w| w.man_start_com(true));
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while !self.regs.intr_status.read().tx_fifo_not_full() {}
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let mut waited = 0;
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while !self.regs.intr_status.read().tx_fifo_not_full() { waited += 1; }
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waited
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}
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}
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}
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}
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@ -234,6 +243,7 @@ impl Flash<()> {
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// Option: Add Feedback Output Clock
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// Option: Add Feedback Output Clock
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// 7. Configure MIO pin 8 for feedback clock.
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// 7. Configure MIO pin 8 for feedback clock.
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// #[cfg(not(feature = "target_zc706"))]
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slcr.mio_pin_08.write(
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slcr.mio_pin_08.write(
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slcr::MioPin08::zeroed()
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slcr::MioPin08::zeroed()
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.l0_sel(true)
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.l0_sel(true)
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@ -272,9 +282,12 @@ impl Flash<()> {
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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baud_rate_div += 1;
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baud_rate_div += 1;
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}
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}
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println!("delay: {:08X}", self.regs.delay.read());
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self.regs.config.write(regs::Config::zeroed()
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self.regs.config.write(regs::Config::zeroed()
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.baud_rate_div(baud_rate_div as u8)
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.baud_rate_div(baud_rate_div as u8)
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.clk_ph(true)
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.clk_pol(true)
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.mode_sel(true)
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.mode_sel(true)
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.leg_flsh(true)
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.leg_flsh(true)
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.holdb_dr(true)
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.holdb_dr(true)
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@ -306,6 +319,7 @@ impl Flash<()> {
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.mode_en(true)
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.mode_en(true)
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// 2 devices
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// 2 devices
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.two_mem(true)
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.two_mem(true)
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.sep_bus(true)
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.u_page(false)
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.u_page(false)
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// Linear Addressing Mode
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// Linear Addressing Mode
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.lq_mode(true)
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.lq_mode(true)
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@ -338,6 +352,11 @@ impl Flash<()> {
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.lq_mode(false)
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.lq_mode(false)
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);
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);
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self.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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self.transition()
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self.transition()
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}
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}
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}
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}
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@ -363,14 +382,28 @@ impl Flash<LinearAddressing> {
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impl Flash<Manual> {
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impl Flash<Manual> {
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pub fn stop(self) -> Flash<()> {
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pub fn stop(self) -> Flash<()> {
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self.regs.enable.modify(|_, w| w.spi_en(false));
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self.transition()
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self.transition()
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}
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}
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pub fn read_reg<R: SpiFlashRegister>(&mut self) -> R {
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pub fn read_reg<R: SpiFlashRegister>(&mut self) -> R {
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let args = Some(R::inst_code());
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let args = Some(R::inst_code());
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let transfer = self.transfer(args.into_iter(), 2)
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let transfer = self.transfer(args.into_iter(), 3)
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.bytes_transfer();
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.bytes_transfer();
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R::new(transfer.skip(1).next().unwrap())
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let b = transfer.skip(1).next().unwrap();
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R::new(b)
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}
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pub fn write_regs(&mut self, sr1: SR1, cr: CR) {
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self.write_enabled(|flash| {
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let args = [
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|
INST_WRR,
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|
sr1.inner,
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|
cr.inner,
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|
];
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flash.transfer(args.into_iter().cloned(), 3);
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});
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}
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}
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|
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pub fn read_reg_until<R, F, A>(&mut self, f: F) -> A
|
pub fn read_reg_until<R, F, A>(&mut self, f: F) -> A
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|
@ -382,10 +415,10 @@ impl Flash<Manual> {
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while result.is_none() {
|
while result.is_none() {
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let args = Some(R::inst_code());
|
let args = Some(R::inst_code());
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for b in self.transfer(args.into_iter(), 32)
|
for b in self.transfer(args.into_iter(), 32)
|
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.bytes_transfer().skip(1) {
|
.bytes_transfer().skip(5) {
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result = f(R::new(b));
|
result = f(R::new(b));
|
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|
|
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if result.is_none() {
|
if result.is_some() {
|
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break;
|
break;
|
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}
|
}
|
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}
|
}
|
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|
@ -395,19 +428,22 @@ impl Flash<Manual> {
|
||||||
|
|
||||||
/// Status Register-1 remains `0x00` immediately after invoking a command.
|
/// Status Register-1 remains `0x00` immediately after invoking a command.
|
||||||
fn wait_while_sr1_zeroed(&mut self) -> SR1 {
|
fn wait_while_sr1_zeroed(&mut self) -> SR1 {
|
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self.read_reg_until::<SR1, _, SR1>(|sr1|
|
println!("wait while sr1 0");
|
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|
let sr1 = self.read_reg_until::<SR1, _, SR1>(|sr1|
|
||||||
if sr1.is_zeroed() {
|
if sr1.is_zeroed() {
|
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None
|
None
|
||||||
} else {
|
} else {
|
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Some(sr1)
|
Some(sr1)
|
||||||
}
|
}
|
||||||
)
|
);
|
||||||
|
println!("sr1 non-zero: {:02X}", sr1.inner);
|
||||||
|
sr1
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Read Identification
|
/// Read Identification
|
||||||
pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
|
pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
|
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let args = Some((INST_RDID as u32) << 24);
|
let args = Some((INST_RDID as u32) << 24);
|
||||||
self.transfer(args.into_iter(), 0x44)
|
self.transfer(args.into_iter(), 0x56)
|
||||||
.bytes_transfer().skip(1)
|
.bytes_transfer().skip(1)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -436,21 +472,23 @@ impl Flash<Manual> {
|
||||||
print!(".");
|
print!(".");
|
||||||
}
|
}
|
||||||
println!("");
|
println!("");
|
||||||
} else {
|
|
||||||
println!("erased? sr1={:02X}", sr1.inner);
|
|
||||||
}
|
}
|
||||||
|
println!("erased? sr1={:02X}", sr1.inner);
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn program<I: Iterator<Item=u32>>(&mut self, offset: u32, data: I) {
|
pub fn program<I: Iterator<Item=u32>>(&mut self, offset: u32, data: I) {
|
||||||
{
|
{
|
||||||
let len = 4 + 4 * data.size_hint().0;
|
let len = 4 + 4 * data.size_hint().0;
|
||||||
|
// let args = Some(SpiWord::W8(INST_PP)).into_iter()
|
||||||
|
// .chain(Some(SpiWord::W24(offset as u32)).into_iter())
|
||||||
|
|
||||||
let args = Some(SpiWord::W32(((INST_PP as u32) << 24) | (offset as u32))).into_iter()
|
let args = Some(SpiWord::W32(((INST_PP as u32) << 24) | (offset as u32))).into_iter()
|
||||||
.chain(data.map(SpiWord::W32));
|
.chain(data.map(SpiWord::W32));
|
||||||
self.transfer(args, len);
|
self.transfer(args, len);
|
||||||
}
|
}
|
||||||
|
|
||||||
// let sr1 = self.wait_while_sr1_zeroed();
|
let sr1 = self.wait_while_sr1_zeroed();
|
||||||
let sr1 = self.read_reg::<SR1>();
|
// let sr1 = self.read_reg::<SR1>();
|
||||||
|
|
||||||
if sr1.e_err() {
|
if sr1.e_err() {
|
||||||
println!("E_ERR");
|
println!("E_ERR");
|
||||||
|
@ -468,10 +506,13 @@ impl Flash<Manual> {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn write_enabled<F: Fn(&mut Self) -> R, R>(&mut self, f: F) -> R {
|
pub fn write_enabled<F: Fn(&mut Self) -> R, R>(&mut self, f: F) -> R {
|
||||||
|
let args = Some(INST_CLSR);
|
||||||
|
self.transfer(args.into_iter(), 1);
|
||||||
// Write Enable
|
// Write Enable
|
||||||
let args = Some(INST_WREN);
|
let args = Some(INST_WREN);
|
||||||
self.transfer(args.into_iter(), 1);
|
self.transfer(args.into_iter(), 1);
|
||||||
self.regs.gpio.modify(|_, w| w.wp_n(true));
|
self.regs.gpio.modify(|_, w| w.wp_n(true));
|
||||||
|
println!("WPn hi");
|
||||||
let sr1 = self.wait_while_sr1_zeroed();
|
let sr1 = self.wait_while_sr1_zeroed();
|
||||||
if !sr1.wel() {
|
if !sr1.wel() {
|
||||||
panic!("Cannot write-enable flash");
|
panic!("Cannot write-enable flash");
|
||||||
|
@ -482,6 +523,7 @@ impl Flash<Manual> {
|
||||||
// Write Disable
|
// Write Disable
|
||||||
let args = Some(INST_WRDI);
|
let args = Some(INST_WRDI);
|
||||||
self.transfer(args.into_iter(), 1);
|
self.transfer(args.into_iter(), 1);
|
||||||
|
println!("WPn lo");
|
||||||
self.regs.gpio.modify(|_, w| w.wp_n(false));
|
self.regs.gpio.modify(|_, w| w.wp_n(false));
|
||||||
|
|
||||||
result
|
result
|
||||||
|
|
|
@ -35,6 +35,18 @@ macro_rules! u8_register {
|
||||||
}
|
}
|
||||||
|
|
||||||
u8_register!(CR, "Configuration Register", 0x35);
|
u8_register!(CR, "Configuration Register", 0x35);
|
||||||
|
impl CR {
|
||||||
|
/// quad I/O mode
|
||||||
|
pub fn quad(&self) -> bool {
|
||||||
|
self.inner.get_bit(1)
|
||||||
|
}
|
||||||
|
|
||||||
|
/// set quad I/O mode
|
||||||
|
pub fn set_quad(&mut self, value: bool) {
|
||||||
|
self.inner.set_bit(1, value);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
u8_register!(SR1, "Status Register-1", 0x05);
|
u8_register!(SR1, "Status Register-1", 0x05);
|
||||||
impl SR1 {
|
impl SR1 {
|
||||||
/// Write In Progress
|
/// Write In Progress
|
||||||
|
|
|
@ -1,6 +1,7 @@
|
||||||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||||
use super::regs;
|
use super::regs;
|
||||||
use super::{SpiWord, Flash, Manual};
|
use super::{SpiWord, Flash, Manual};
|
||||||
|
use crate::{print, println};
|
||||||
|
|
||||||
pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
|
pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
|
||||||
flash: &'a mut Flash<Manual>,
|
flash: &'a mut Flash<Manual>,
|
||||||
|
@ -13,10 +14,6 @@ pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
|
||||||
impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
||||||
pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self {
|
pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self {
|
||||||
flash.regs.config.modify(|_, w| w.pcs(false));
|
flash.regs.config.modify(|_, w| w.pcs(false));
|
||||||
flash.regs.enable.write(
|
|
||||||
regs::Enable::zeroed()
|
|
||||||
.spi_en(true)
|
|
||||||
);
|
|
||||||
|
|
||||||
let mut xfer = Transfer {
|
let mut xfer = Transfer {
|
||||||
flash,
|
flash,
|
||||||
|
@ -35,13 +32,15 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
||||||
let arg = self.args.next()
|
let arg = self.args.next()
|
||||||
.map(|n| n.into())
|
.map(|n| n.into())
|
||||||
.unwrap_or(SpiWord::W32(0));
|
.unwrap_or(SpiWord::W32(0));
|
||||||
match arg {
|
|
||||||
|
// println!("w {:?}", arg);
|
||||||
|
let write_len = match arg {
|
||||||
SpiWord::W32(w) => {
|
SpiWord::W32(w) => {
|
||||||
// println!("txd0 {:08X}", w);
|
// println!("txd0 {:08X}", w);
|
||||||
unsafe {
|
unsafe {
|
||||||
self.flash.regs.txd0.write(w);
|
self.flash.regs.txd0.write(w);
|
||||||
}
|
}
|
||||||
self.sent += 4;
|
4
|
||||||
}
|
}
|
||||||
// Only txd0 can be used without flushing
|
// Only txd0 can be used without flushing
|
||||||
_ => {
|
_ => {
|
||||||
|
@ -50,32 +49,38 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
||||||
self.flash.wait_tx_fifo_flush();
|
self.flash.wait_tx_fifo_flush();
|
||||||
}
|
}
|
||||||
|
|
||||||
match arg {
|
let write_len = match arg {
|
||||||
SpiWord::W8(w) => {
|
SpiWord::W8(w) => {
|
||||||
// println!("txd1 {:02X}", w);
|
// println!("txd1 {:02X}", w);
|
||||||
unsafe {
|
unsafe {
|
||||||
self.flash.regs.txd1.write(u32::from(w) << 24);
|
self.flash.regs.txd1.write(u32::from(w) << 24);
|
||||||
}
|
}
|
||||||
self.sent += 1;
|
1
|
||||||
}
|
}
|
||||||
SpiWord::W16(w) => {
|
SpiWord::W16(w) => {
|
||||||
unsafe {
|
unsafe {
|
||||||
self.flash.regs.txd2.write(u32::from(w) << 16);
|
self.flash.regs.txd2.write(u32::from(w) << 16);
|
||||||
}
|
}
|
||||||
self.sent += 2;
|
2
|
||||||
}
|
}
|
||||||
SpiWord::W24(w) => {
|
SpiWord::W24(w) => {
|
||||||
unsafe {
|
unsafe {
|
||||||
self.flash.regs.txd3.write(w << 8);
|
self.flash.regs.txd3.write(w << 8);
|
||||||
}
|
}
|
||||||
self.sent += 3;
|
3
|
||||||
}
|
}
|
||||||
SpiWord::W32(_) => unreachable!(),
|
SpiWord::W32(_) => unreachable!(),
|
||||||
}
|
};
|
||||||
|
|
||||||
self.flash.wait_tx_fifo_flush();
|
self.flash.wait_tx_fifo_flush();
|
||||||
|
|
||||||
|
write_len
|
||||||
}
|
}
|
||||||
}
|
};
|
||||||
|
self.sent += write_len;
|
||||||
|
// if self.sent % 258 == 0 {
|
||||||
|
// self.flash.wait_tx_fifo_flush();
|
||||||
|
// }
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -85,6 +90,7 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
||||||
|
|
||||||
fn read(&mut self) -> u32 {
|
fn read(&mut self) -> u32 {
|
||||||
let rx = self.flash.regs.rx_data.read();
|
let rx = self.flash.regs.rx_data.read();
|
||||||
|
// println!("r 0x{:02X}", rx);
|
||||||
self.received += 4;
|
self.received += 4;
|
||||||
rx
|
rx
|
||||||
}
|
}
|
||||||
|
@ -97,15 +103,21 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args,
|
||||||
self.read();
|
self.read();
|
||||||
}
|
}
|
||||||
|
|
||||||
// Stop
|
// // Stop
|
||||||
self.flash.regs.enable.write(
|
// self.flash.regs.enable.write(
|
||||||
regs::Enable::zeroed()
|
// regs::Enable::zeroed()
|
||||||
.spi_en(false)
|
// .spi_en(false)
|
||||||
);
|
// );
|
||||||
|
|
||||||
self.flash.regs.config.modify(|_, w| w
|
self.flash.regs.config.modify(|_, w| w
|
||||||
.pcs(true)
|
.pcs(true)
|
||||||
.man_start_com(false)
|
.man_start_com(false)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
/// Leave PCS high for a few cycles
|
||||||
|
for _ in 0..0x100 {
|
||||||
|
libcortex_a9::asm::nop();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -119,7 +131,10 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Iterator for Transfer<'a, A
|
||||||
|
|
||||||
self.fill_tx_fifo();
|
self.fill_tx_fifo();
|
||||||
|
|
||||||
|
// print!("read:");
|
||||||
while !self.can_read() {}
|
while !self.can_read() {}
|
||||||
Some(self.read())
|
let b = self.read();
|
||||||
|
// println!(" {:08X}", b);
|
||||||
|
Some(b)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue